PCI Express PHY IP Listing

PCIe is the most common protocol in high speed serial standards to connect components in embedded systems.

• TSMC
• 12nm
• FFC

PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.

• UMC
• 180nm
• G

PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY, UMC 0.18um GII Logic (RVT) process.

• UMC
• 180nm
• G

The PCIe 5.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 5.0/4.0/3.0, and PIPE specific…

• PCI Express

We propound best in class fully customizable PCIe 3.0 PHY, targeted for both enterprise and client application, the complaint to …

• Single-Protocol PHY

The TRC16024CPA is a four lane Gen 1,2,3,4 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transm…

• TSMC
• 16nm

The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…

• Single-Protocol PHY
• Now

The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…

• TSMC
• 2nm
• N2P

Intel defined the PHY Interface for PCI Express (PIPE) as a standard interface between a PHY device and the Media Access (MAC) la…

• Single-Protocol PHY

MSquare's PCI Express 4.0 PHY IP includes a high-speed, -efficient, and cost-effective transceiver to turbocharge today's high-pe…

• Single-Protocol PHY

SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling.

• Single-Protocol PHY
• Please contact the provider for test chip availability
• now
• PCIe Base Specification 1.0…

4x lane PCI Express Gen II PHY, UMC 90nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP

PCI-Express II PHY, UMC 90nm SP/RVT Low-K process.

• UMC
• 90nm
• SP

PCIE Gen.II, UMC 55nm SP/RVT Low-K Logic process.

• UMC
• 55nm
• SP

The IP for PCI Express® to ARM® AMBA® 3 AXI/4 AXI Bridge enables designers who use the AMBA 3 AXI or 4 AXI interconnect on-chip b…

• Protocol Bridge

The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…

• Samsung
• 28nm
• FDS
• Silicon Proven

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• TSMC
• 40nm
• G

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports…

• Samsung
• 8nm
• 8LPP

The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).

• Samsung
• 8nm
• 8LPP