Embedded FPGA IP Listing

SPC (Synthesizable Programmable Core) is a soft FPGA core that is fully integrated into standard design flows and that allows the…

• eFPGA
• In production since 2012
• Immediate

Speedcore embedded FPGA (eFPGA) IP has brought the performance and flexibility of programmable logic to ASICs and SoCs.

• eFPGA

The DB-I2C-M-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus.

• I2C / I3C

The DB-I2C-MS-AVLN Controller IP Core interfaces a microprocessor via the Avalon Bus to an I2C Bus in Standard-Mode (100 Kbit/s) …

• I2C / I3C

The IntelliProp SATA Host AHCI (IPC-SA156A-HI) is an industry standard Serial-ATA (SATA) host interface core that enables custome…

• SATA Controller

USB is a generic interface in the modern days to connect to various high speed data peripherals.

• USB

The LMB module is used as the LMB interconnect for Xilinx FPGA based embedded processor systems.

• Bus Fabric

Generation of clock signal with a fixed but programmable phase difference with respect to a reference input clock is critical in …

• DLL

Flash memory forms a basic constituent in many FPGA based embedded systems using Xilinx SRAM based FPGAs.

• Protocol Bridge

Centar's DFT circuit can perform all 35 transform sizes needed to implement the LTE SC-FDMA protocols.

• Filters Transforms
• Hardware verified
• Now
• LTE SC-FDMA

This FFT circuit employs unique architectural characteristics providing functionality and capabilities not possible with other FF…

• Filters Transforms
• Verified
• Now

The transform computation is based on a new matrix formulation of the discreet Fourier transform1 (DFT) which decomposes it into …

• Filters Transforms
• Hardware verified
• Now

This FFT circuit employs unique architectural characteristics, different than any other FFT implementation.

• Filters Transforms
• Hardware verified
• Now

The TSN-SE implements a configurable controller meant to ease the implementation of switched endpoints for Time Sensitive Net-wor…

• Ethernet

The MPEG-2 Decoder Core is a high performance and high quality solution video decompression engine targeted primarily at FPGAs.

• Video Processing

Scan Ring Linker enables multiple 1149.1 scan rings

• Test / Debug
• NOW – ASIC Q203

The DB9000AXI4-UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Int…

• Display Controller

MicroBlaze™ is a 32-bit RISC soft processor core that can be used with soft peripherals to design embedded systems in Xilinx FPGA…

• MCU

The DB-UDP-IP-1GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 1 GbE…

• Ethernet
• Successful in Company FPGA Kit Demo Reference Design, Customer Products
• Immediately
• 802.3 Ethernet MAC, UDP, IP

The DB-UDP-IP-10GbE-AMBA is a UDP/IP Hardware Stack / UDP Off load Engine (UOE) with low latency, high-performance targeting 10 G…

• Ethernet
• Successful in Company FPGA Kit Demo Reference Design, Customer Products
• Immediately
• 802.3 Ethernet MAC, UDP, IP