SmartDV Technologies
•
HQ:
India
DDR Memory Model provides an smart way to verify the DDR component of a SOC or a ASIC.
- DDR
Compare 580 DDR Memory IP Listing from 69 vendors
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DDR Memory Controller IP for low power and high reliability
T2M GmbH• HQ: UnknownDDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Sp…
- DDR
- In Production
- Immediately
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Avalon Mobile DDR Memory Controller
Microtronix Datacom Ltd.• HQ: CanadaThe Microtronix Avalon Mobile DDR SDRAM Memory Controller IP Core is designed for building high-performance Avalon-MM / Avalon-ST…
- DDR
- Available for immediate sale
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DO-254 DDR Memory Controller 1.00a
Logicircuit, Inc.• HQ: USAA dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the …
- DDR
- 2014
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PLL general purpose / DDR memory, 50-500Mhz, 4 phases (0/90/180/270)
V-Trans Microelectronics• HQ: CHINAThe VT18PLL500 is a macro cell for clock generation.
- PLL
- silicon proven
- now
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Synopsys, Inc.• HQ: USA
The Gen 2 DDR multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard LPDDR2, LPDDR3…
- Single-Protocol PHY
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Synopsys, Inc.• HQ: USA
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- DDR
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DDR Enhanced Protocol Controller (uPCTL2) supporting DDR4, DDR3, DDR2, LPDDR4, LPDDR3, and LPDDR2
Synopsys, Inc.• HQ: USAThe Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- DDR
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NVMe IP core -- Directly connect PCIe SSD without external memory
Design Gateway Co., Ltd.• HQ: ThailandNVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handl…
- NVMe Controller
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Synopsys, Inc.• HQ: USA
The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3 and DDR2 SDRAM memor…
- TSMC
- 40nm
- LP
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Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- Single-Protocol PHY
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Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- UMC
- 28nm
- HPC
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Synopsys, Inc.• HQ: USA
The DDR4 multiPHY IP cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR4, DDR3, LPDDR2,…
- TSMC
- 28nm
- HPC+
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Synopsys, Inc.• HQ: USA
The Enhanced Universal DDR Controllers consist of two high-performance products: the Enhanced Universal DDR Memory Controller (uM…
- DDR
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tRoot Vx Hardware Secure Modules
Synopsys, Inc.• HQ: USAThe tRoot™ Hardware Secure Modules (HSMs) with Root of Trust enable connected devices to securely and uniquely identify and authe…
- Root Of Trust
- Available on request
- Available
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IObundle, Lda• HQ: Portugal
IOb-SoC is a RISC-V SoC template written in Verilog, which users can download for free, modify, simulate and implement in FPGA or…
- CPU
- FPGA-proven
- Now
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HCL Technologies• HQ: India
The AXI DDR3 Controller provides access to DDR3 memory.
- DDR
- Soft Core
- Now
- AMBA AXI 3.0
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Xylon• HQ: Croatia
The logiHSSL IP core enables high-speed communication between microcontrollers of Infineon's AURIX family (TC2xx and TC3xx) and X…
- Interlaken
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Atria Logic, Inc.• HQ: USA
The AL_EMAC_CORE Ethernet MAC Core is hardware implementation of Ethernet protocol defined by IEEE 802.3-2005 Specification.
- Ethernet
- Now
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MVD Cores• HQ: France
The MVD ISDB-T core is a drop-in module that includes the following functions : • Input data framer from DVB-SPI source (MPEG-TS …
- Modulation Demodulation
- June 2016
- ARIB STD-B31