eMMC PHY IP Listing

Dolphin Technology delivers custom, synthesizable IP to support specific design requirements.

• SD / eMMC Controller
• Pre Silicon
• Yes

This IP integrates both xSPI (Expanded Serial Peripheral Interface) and eMMC 5.1 PHY (Physical Layer) into a single unified solut…

• SPI / QSPI XSPI

The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification.

• Single-Protocol PHY

The SD/EMMC PHY IP supports up to 208MHz which compliant with SDIO and EMMC specification.

• Single-Protocol PHY

The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering…

• TSMC
• 22nm
• ULL
• Available on request

The eMMC/SD/SDIO Combo IP is a comprehensive solution designed to support high-performance storage and I/O connectivity for a wid…

• SD / eMMC Controller

MSquare offers a silicon-proven ONFI 5.0 PHY IP that supports all modes of the Open NAND Flash Interface (ONFI) 5.0 specification.

• Single-Protocol PHY

The SD/eMMC Host Controller IP Core implements the SD Physical Layer v3.0 and eMMC Physical Layer v4.51 compatible Host Controlle…

• SD / eMMC Controller
• Now

iW-PCIe to SD/MMC Bridge is the IP core which converts the PCIe to SD or MMC bus interface.

• PCI Express
• Not Applicable
• Available
• FPGA IP Core

SDIO protocol is evolved and upgraded from the SD card protocol.

• SD / eMMC Controller

The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a integrated host controller IP solution that supports three key…

• SD / eMMC Controller

The SD 4.1/SDIO 4.1 IP from Arasan Chip Systems is a integrated host controller IP solution that supports three key memory card I…

• SD / eMMC Controller

The eMMC 5.1 Device I/O is verified to be fully compliant I/O interface for JEDEC eMMC 5.1 when rectified and eMMC 5.0 JESD84-B50…

• High-Speed

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 5nm
• N5A

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 3nm
• N3P

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 3nm
• N3P

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 3nm
• N3E

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• TSMC
• 3nm
• N3A

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• Samsung
• 8nm

Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions.

• Samsung
• 8nm