The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
- CXL
- Available
- CXL, PCI-SIG
The Compute Express Link® (CXL®) 3.1 Controller is a parameterizable design for ASIC and FPGA implementations.
CXL (Compute eXpress Link) 3.1 IP
The Panmnesia Compute Express Link (CXL) IP implements all necessary logic for CXL device, host, and switch.
Low-latency Controller IP for cache-coherent root-port, end-point, and dual-mode applications The Controller IP for CXL addresses…
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b with AMBA bridge for CXL.io
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Premium Controller EP/RP/DM 1024b/512b/256b/128b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge and Advanced HPC Features (Arm CCA)
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge + LTI and MSI-GIC interfaces
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b with AMBA bridge
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 2.0 Premium Controller Device/Host/DM 512b
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
Adds security Interfaces, features to CXL 3.0 Premium controllers
The Compute Express Link (CXL) Controller IP implements the port logic required to build a CXL device, host or switch, and can be…
CXL 3.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general…
PCIe 6.0 / CXL 3.0 PHY & Controller
The PCIe 6.0 and CXL 3.0 IP solutions combine high-performance controllers and PHYs, fully compliant with PCIe 6.0, CXL 3.0, and …
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/…
PCIe 5.0 PHY NCS in TSMC (N7, N6, N5)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to mee…
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N5, N4P, N3E, N3P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to mee…
PCIe 5.0 PHY, NCS, TSMC N7 x1, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY NCS, TSMC N7 x4, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …
PCIe 5.0 PHY, TSMC N6 x6, North/South (vertical) poly orientation
The multi-channel PHY IP for PCI Express® (PCIe®)5.0 and CXL includes a high-speed, high-performance transceiver to meet today’s …