Purpose-built AI model compression IP, combining software compression with hardware decompression for static model data and hardw…
- Data Compression
Purpose-built AI model compression IP, combining software compression with hardware decompression for static model data and hardw…
Hardware compressed memory IP for CXL devices and chip-to-chip links
Hardware compressed memory IP for CXL devices, with inline compression plus complete memory management
Hardware link (de)compression IP for die-to-die, chip-to-chip, and DRAM interfaces
Expands effective bandwidth across links and memory interfaces with deterministic, data-independent latency, fully pipelined to sustain line rate
LZ4-compatible hardware compressor and decompressor IP
Standards-based, LZ4-compatible hardware compressor and decompressor for storage and SSD controllers.
InfiniNoC is a highly customizable interconnect fabric designed to provide a scalable, high-performance communication backbone for next-generation SoCs.