PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
- Samsung
- 8nm
- 8LPP
PCI Express Gen5 SERDES PHY on Samsung 8LPP
The Programmable SERDES provides a Physical Media Attachment (PMA) Layer and synthesizable Physical Coding Sublayer (PCS).
The PCIe 5.0 Multi-port Switch (formerly XpressSWITCH) is a customizable, multiport embedded Switch for PCIe designed for ASIC an…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN7FF
The PCIe Gen5 REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Ex…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3P-CLN3X
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN3E
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN2P
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5 Ref Clock SSCG PLL on GLOBALFOUNDRIES 12LP+
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
The PCIe REF PLL addresses stringent performance requirements in high-speed serial link applications that support the PCI Express…
PCIe Gen4/5/6 Class Low Jitter LC PLL on TSMC CLN6FF
The PCIe Gen5 Ref Clock SSCG PLL addresses stringent performance requirements in high-speed serial link applications that support…
The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and eas…
The PCIe 5.0 Controller is designed to achieve maximum PCI Express® (PCIe®) 5.0 performance with great design flexibility and eas…
The PCIe Gen 5 Verification IP provides an effective & efficient way to verify the components interfacing with PCIe Gen 5 interfa…
PCIe 5.0 (Gen5) Standard Controller with AMBA bridge II
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits with AMBA bridge
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
PCIe 5.0 (Gen5) Standard Controller EP/RP/DM/SW 32-128 bits
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
PCIe 5.0 (Gen5) Premium Controller with AMBA bridge II
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
PCIe 5.0 (Gen5) Premium Controller II
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
PCIe 5.0 (Gen5) Premium Controller EP/RP/DM/SW 32-512 bits with AMBA bridge
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…
PCIe 5.0 (Gen5) Premium Controller EP/RP/DM/SW 32-512 bits
The configurable and scalable the Controller IP for PCI Express® (PCIe®) supports all required features of the PCI Express 5.0, 4…