Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
- Register File
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
ROM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous VIA2 programmed ROM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process synchronous high density Two Port (1R1W) SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Single Port SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous high density Two Port (1R1W) SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.35um process
UMC 0.35um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.3um HV process
UMC 0.3um HV process Core Cell Library.
IP
Voltage Detector IP, 4 Levels, HJTC 0.18um eFlash/G2 process
4-level detector for USB applications, input 3.3V, Ivcca=115uA, HJTC 0.18um embedded flash (P-channel cell) process.
USB 2.0 Device PHY IP, Non-Crystal mode support, HJTC 0.11um pFlash/LL process
USB2.0 PHY, crystal-less, HJ 0.11um pflash LL process.
USB 1.1.OTG PHY IP, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process, USB 1.1 OTG.
Standard Cell (MiniLib) Library IP, 7 tracks, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process Mini-Library.
Standard Cell (Generic) Library IP, RTC Cell, HJTC 0.18um eFlash/G2 process
HJ 0.18um eFlash process RTC Standard Cell Library.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.162um eFlash/LL process
UMC 0.162um eFlash/LL 9-Track Generic Core Cell Library.