12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
- 12 Bit
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HLMC 55nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HLMC 55nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HHGrace 110nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HLMC 55nm
12-Bit 1MSPS SAR ADC, 10.5 Bit ENOB - HLMC 55nm
12-Bit IQ 100MSPS SAR ADC, ENOB: 9.5Bit - SMIC 28nm
12-Bit IQ 100MSPS SAR ADC, ENOB: 9.5Bit - SMIC 28nm
24-Bit Stereo Audio ADC, SNR>95dB - HLMC 55nm
24-Bit Stereo Audio ADC, SNR>95dB - HLMC 55nm
The SpaceWire IP core is compliant with the IEEE 1355 standard.
CCSDS 121/123 Lossless Compression
The GRSHYLOC IP enables lossless compression for multi-spectral and hyper-spectral images according to the CCSDS121 and CCSDS123 …
HOTLink II IP Core
It supports standard I3C, high-speed I3C, and Ultra-higher-speed I3C modes.
IP
Verilog IP for connecting to an External Hyperbus Memory chip.
Silterra 0.11um Ultra Low Leakage 6track PMK Library
IP
GLOBALFOUNDARIES 22nm FDSOI USB3.0 Dual Role PHY/OTG PHY
This USB3.0 PHY IP is designed according to USB3.0 and USB2.0 specification.
A single DCDC converter that can generate all the power supplies from a Li+ battery for a typical SoC or mixed signal IC.
Linear Li+ charger with standard trickle, CC and CV charging
Process monitoring for NVT and SubVt operations
Power switches ultra low leakage requirements
ESD And IO Pads