USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process.
- USB 3.0
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB 3.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB3.0 OTG PHY, UMC 0.13um HS/FSG Logic process.
USB 3.0 OTG PHY IP, UMC 0.11um HS/FSG process
USB3.0 PHY, UMC 0.11um HS/FSG (Cu) Logic process.
USB 3.0 OTG PHY IP, UMC 0.11um HS/AE process
USB3.0 PHY, UMC 0.11um HS/AE Logic process.
USB 2.0 OTG PHY IP, UMC 90nm LL process
USB2.0 OTG PHY, UMC 90nm LL Low-K -RVT process 2.5V OD 3.3V.
USB 2.0 OTG PHY IP, UMC 90nm SP process
USB2.0 OTG PHY, UMC 90nm SP/RVT/ Low-K process.
USB 2.0 OTG PHY IP, UMC 65nm LP process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm LP/RVT Low-K Logic process.
USB 2.0 OTG PHY IP, UMC 65nm LL process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 65nm low leakage RVT Low-K process.
USB 2.0 OTG PHY IP, UMC 65nm SP process
USB2.0 OTG (VDT and ID are included in PHY), UMC 65nm SP/HVT Low-K process.
USB 2.0 OTG PHY IP, UMC 55nm SP process
OTG USB 2.0 PHY (VDT and ID are included in PHY), UMC 55nm SP Low-K Logic process.
USB 2.0 Device PHY IP, UMC 0.18um CIS process
USB2.0 PHY, UMC 0.18um CMOS Image Sensor process.
USB 2.0 OTG PHY IP, UMC 0.18um eFlash/G2 process
USB2.0 OTG PHY, UMC 0.18um eFlash process.
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 PHY, UMC 0.18um GII Logic process.
USB 2.0 OTG PHY IP, UMC 0.18um eFlash/G2 process
USB2.0 OTG PHY, UMC 0.18um E-flash process.
USB 2.0 Device PHY IP, UMC 0.13um CIS process
USB 2.0 PHY, UMC 0.13um CMOS Image Sensor process.
USB 2.0 Device PHY IP, UMC 0.11um LL/FSG process
USB 2.0 PHY, UMC 0.11um LL Logic process.
USB 2.0 Device PHY IP, UMC 0.11um HS/FSG process
USB 2.0 PHY, UMC 0.11um HS Logic process.
USB 2.0 Device PHY IP, UMC 0.11um HS/AE process
USB 2.0 PHY, UMC 0.11um HS/AE standard Logic process.
USB 2.0 OTG PHY IP, OTG, UMC 0.11um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.11um HS/FSG Logic process.
USB 2.0 OTG PHY IP, OTG, UMC 0.11um HS/AE process
USB 2.0 OTG PHY, UMC 0.11um HS AL Logic process.
USB 2.0 OTG PHY IP, UMC 0.11um HS/AE process
USB 2.0 OTG PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process.