Linear Regulator IP, Input: 3.3V, Output: 1.1V/200mA, UMC 40nm LP process
3.3V to 1.1V/200mA REG, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.
- UMC
- 40nm
- LP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Linear Regulator IP, Input: 3.3V, Output: 1.1V/200mA, UMC 40nm LP process
3.3V to 1.1V/200mA REG, Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.
Linear Regulator IP, Input: 3.3V, Output: 1.1V/150mA, UMC 40nm LP process
3.3V to 1.1V with 150mA driving capability, High accuracy Non-trim Linear Regulator, UMC 40nm LP/RVT Low-K Logic process.
Voltage Detector IP, Vdet: 2.5V, UMC 0.11um HS/FSG process
Voltage Detect Vdet=2.5V Vhys=0.1V, generate a high/low level Logic for a precise power supply monitoring system, UMC 0.11um HS/F…
Voltage Detector IP, 4 Levels, UMC 40nm LP process
4-Level Voltage Detector for USB-OTG, UMC 40nm 2.5V overdrive 3.3V device LP/RVT Logic process.
Voltage Detector IP, 4 Levels, UMC 0.11um HS/AE process
4-level detector for USB-OTG applications, input 3.3V, UMC 0.11um HS/AE Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V, Vfr=2.0V, B type IO, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.11um HS/AE process
Vrr=2.2V, Vfr=2.0V, A type IO, 3.3V Power On Reset, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Power on Reset IP, Input: 2.5V, UMC 40nm LP process
Vrr=2.0V Vfr=1.9V, VCC3I=2.5V, 2.5V Power On Reset, special request, UMC 40nm LP/RVT Low-K Logic process.
Power on Reset IP, Input: 2.5V, UMC 40nm LP process
2.5V Power On Reset, Vrr=1.90 without Vfr, UMC 40nm LP/RVT Low-K Logic process.
Power on Reset IP, Input: 1.0V/3.3V, UMC 40nm LP process
Vrr=2.33V Vfr=2.26V, input VCCK=1.0V VCC3IO=3.3V, 3.3V Power On Reset, special request, UMC 40nm LP/RVT Low-K Logic process.
PLL (Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/FSG process
5GHz SSCG with 25MHz reference clock, UMC 0.11um 20T HS/FSG Logic process.
PLL (Spread Spectrum) IP, 20MHz - 70MHz, UMC 0.18um G2 process
UMC 0.18um GII Logic process 20MHz-70MHz delay-type spread-spectrum clock generator.
Input clock range:10M ~ 1280MHz, output clock range:15.625M ~ 2000MHz wide-range SSCG, UMC 0.11um HS/AE (AL Enhancement) 2T Logic…
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
PLL (All Digital, Spread Spectrum) IP, Input: 25MHz, Output: 5GHz, UMC 0.11um HS/AE process
5GHz SSCG with 25MHz reference clock, UMC 0.11um HS/AE (AL Enhancement) 2T Logic process.
Input 80M-150MHz, output 80M-150MHz, frequency synthesizable PLL, UMC 0.13um Logic EHS/FSG process.
PLL (Frequency Synthesizer) IP, Input: 66MHz - 100MHz, Output: 400MHz - 800MHz, UMC 90nm SP process
Input 66M-100MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 90nm SP Logic process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 300MHz, Output: 20MHz - 300MHz, UMC 90nm LL process
Input 5M-300MHz, output 20M-300MHz, frequency synthesizable PLL, UMC 90nm LL/RVT process.
PLL (Frequency Synthesizer) IP, Input: 25MHz - 66MHz, Output: 400MHz - 800MHz, UMC 55nm LP process
Input 25M-66MHz, output 400M-800MHz, frequency synthesizable PLL, UMC 55nm LP/RVT Low-K Logic process.