SMIC 40nm Low Leakage HD, channel length 50nm, LVT Logic Process Standard cell Library
- SMIC
- 40nm
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SMIC 40nm Low Leakage HD, channel length 50nm, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 50nm, HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, RVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, PMK,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, PMK,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, HVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,RVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,RVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,LVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,LVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, ECO,HVT Logic Process Standard cell Library
SMIC 40nm Low Leakage HD, channel length 40nm, ECO,HVT Logic Process Standard cell Library
40nm Low Leakage HD, Channel Length 40nm, A12T PEK LVT Logic Process Standard Cell Library
SMIC 40nm Low Leakage A12T PEK LVT Logic Process Standard Cell Library
IP
32.768KHz Low-Power Oscillator IO
IP
2Kbit Efuse with parallel input and parallel output
Program Voltage:2.5V, Program Temperature:10~40 degrees, 2Kbit Efuse with parallel input and parallel output
256bit Efuse with parallel input and parallel output
Program Voltage:2.5V, Program Temperature:10~40 degrees, 256bit Efuse with parallel input and parallel output
1Kbit Efuse with parallel input and parallel output
Program Voltage:2.5V, Program Temperature:10~40 degrees, 1Kbit Efuse with parallel input and parallel output
1.1V, Max frequency 1.5GHz PLL
1.1V, Max frequency 1.5GHz
1.1/3.3V 10bit 54M 1 channel DAC
1.1/3.3V 10bit 54M 1channel
1.1/3.3V 10bit 2MSPS 8 channel ADC
1.1/3.3V 10bit 2MSPS 8channel
1.1/3.3V 10bit 200KSPS 8 channel ADC
1.1/3.3V 10bit 200KSPS 8channel
1.1/3.3V 10bit 1MSPS 8 channel ADC
1.1/3.3V 10bit 1MSPS 8channel