Single Port SRAM Compiler IP, UMC 40nm LP process
ULL Single Port SRAM with row redundancy, UMC 40nm LP process.
- UMC
- 40nm
- LP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Single Port SRAM Compiler IP, UMC 40nm LP process
ULL Single Port SRAM with row redundancy, UMC 40nm LP process.
Single Port SRAM Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT Single Port SRAM compiler with Power Gating & row redundancy.
Single Port SRAM Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT Single Port SRAM compiler with peripheral LVT and Power Gating.
Single Port SRAM Compiler IP, UMC 40nm LP process
ULL Single Port SRAM, UMC 40nm LP process.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP process LVT synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process LVT synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP process standard LVT synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process LVT synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
UMC 28nm HLP process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 28nm HLP process
high density Single Port SRAM, UMC 28nm HLP process.
Single Port SRAM Compiler IP, UMC 0.25um SP process
UMC 0.25um Logic process synchronous high speed Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Single Port Low Power SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.25um process
UMC 0.25um Logic process standard asynchronous low density Low Power Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high speed , UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high speed Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, 4.0um2 bit cells, High density, Low Power, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous high density, Low Power mini Single Port SRAM.