USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
- USB 2.0
- UMC
- 130nm
- HS
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
USB 2.0 OTG PHY IP, UMC 0.13um HS/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um HS/FSG Logic process.
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 Analog PHY, UMC 0.18um GII Logic RVT/FSG process.
USB 2.0 Device PHY IP, UMC 0.18um G2 process
USB2.0 PHY (Pure device mode), UMC 0.18um GII Logic RVT/FSG process.
USB 2.0 Device PHY IP, UMC 0.13um LL/FSG process
USB 2.0 PHY, UMC 0.13um LL Logic process.
USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 40nm LP process
USB 2.0 PHY, crystal-less option, UMC 40nm LP/RVT process.
USB 1.1.OTG PHY IP, UMC 0.13um HS/FSG process
0.13um OTG PHY, UMC 0.13um HS/FSG process.
USB 1.1 PHY IP, UMC 0.18um G2 process
USB 1.1 transceiver, UMC 0.18um GII Logic process.
USB 1.1 PHY IP, UMC 0.18um G2 process
USB 1.1 PHY, UMC 0.18um GII Logic process 1.8/3.3V.
Two Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP Logic Low-K process synchronous Two Port (1R1W) Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 55nm LP process
UMC 55nm LP/ Low-K process PG Two Port Register File compiler.
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP Two Port Register File with Sleep/Retention/Nap mode feature.
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/LVT process, Two Port Register File with LVT.
Two Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP/ Low-K process, Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP peripheral LVT Two Port Register File memory compiler.
Two Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K Two Port Register File compiler.
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous low density Low Power Two Port (1R1W) SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Two Port Register File compiler.
Two Port Register File Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous Two Port Register File SRAM memory compiler.
Two Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um Logic HS FSG Synchronous high density Low Power Two Port Register File SRAM memory compiler.