GSMC 0.25um process 2.5v/3.3v Generic IO library
- GPIO
- Silicon proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
GSMC 0.25um process 2.5v/3.3v Generic IO library
GSMC 0.18um ULL process 1.8v/3.3v Generic IO library
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/5v Generic IO library
GSMC 0.18um cost effective IO Library
GSMC 0.18um G9 process 3.3v/3.3v Generic IO library
GSMC 0.18um LP process 1.8v/3.3v Generic IO library
GSMC 0.18um process 1.8v/3.3v Generic IO library
GSMC 0.16um process 1.8v/3.3v Generic IO library
GSMC 0.15um process 1.5v/3.3v Generic IO library
GSMC 0.15um ULP process 1.8v/2.8v Generic IO library
GSMC 0.15um LV process 1.5v/3.3v Generic IO library
GSMC 0.15um LP process 1.5v/3.3v Generic IO library
GSMC 0.14um LV process 1.2v/3.3v Generic IO library
Virtex 7 GTX SATA 3 Host Controller
The LDS SATA 3 HOST XV7X IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 7 GTX speed gra…
Linear Regulator IP, UMC 0.18um G2 process
Input 2.7V~3.6V, Output=1.8V,Loading 50mA Regulator, UMC 0.18um GII 1.8V/3.3V Process
Standard Cell (Generic) Library IP, UMC 0.13um process
UMC 0.13um Logic process, DFY Cell Library.
Linear Regulator IP, UMC 0.11um HS/AE process
3.3V to 1.2V Capacitor-Free Linear Regulator with 100mA driving capability, UMC 0.11um HS/AE (AL Enhancement) Logic Process
USB 2.0 Device PHY IP, UMC 0.11um eFlash process
UMC 0.11um eFlash Process , USB 2.0 OTG PHY
1.0~3.6V input, loading 20mA, 0.9V output with VBG=0.75V Linear Regulator, UMC 55nm ULP/UHVT Low-K Logic Process
Input 1.0V-3.6V, VBG=0.75V, Band Gap, UMC 55nm ULP Low-K Logic process
Standard Cell (RTC) Library IP, UMC 55nm ULP process
UMC 55nm ULP/uHVT LowK Logic Process 2.5 V OD 3.3 V device RTC Core Library