USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB 3.1 PHY (10G/5G) in Samsung (14nm, 11nm, 10nm, 8nm, SF5, SF5A, SF4E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB-C 3.1/DP TX PHY in Samsung (14nm, 11nm, 5nm)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
USB-C 3.1/DP TX PHY in TSMC (16nm, 12nm, N7, N6)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum.
AXI Performance Subsystem - ARM Cortex A
The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needin…
MIPI DSI-2 V2 Host Controller Prem
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
MIPI DSI-2 V2 Host Controller ASIL Compliant
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
MIPI DSI-2 High Performance Device Controller
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
MIPI DSI-2 High Performance Device Combo Controller for Automotive
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
MIPI DSI-2 High Performance Device Combo Controller
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
MIPI DSI Host Combo Controller
The MIPI® DSI/DSI-2 Host and Device Controller IP solutions are fully verified and configurable controllers that implement all th…
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N5, N3)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.0 D-PHY v1.2 RX 2 trios/2 Lanes in TSMC (12nm, N5)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3E)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband proce…