SMIC 0.18um Low Leakage 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.18um Low Leakage 9T High-Density Standard Cell Library
- SMIC
- 180nm
- G
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
SMIC 0.18um Low Leakage 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.18um Low Leakage 9T High-Density Standard Cell Library
SMIC 0.18um 3.3V Standard Cell Library,3.3v operating voltage
SMIC 0.18um 3.3V Standard Cell Library
SMIC 0.18um Isolation Cell Library,1.8v operating voltage
SMIC 0.18um Isolation Cell Library
SMIC 0.18um 1.8V<->3.3V level shifter,1.8v/3.3vv operating voltage
SMIC 0.18um 1.8V3.3V Level Shfiter Library
SMIC 0.18um 7 track High Density Standard Cell Library,1.8v operating voltage
SMIC 0.18um 7T High-Density Standard Cell Library
SMIC 0.18um 9 track Standard Cell Library,1.8v operating voltage
SMIC 0.18um 9T High-Density Standard Cell Library
IP
IP
USB1.1 PHY - HHGrace 110nm ULL
IP
IP
IP
Cost Efficient and Low-Power Design for MCUs, Wearables, and AIoT Devices
Motion JPEG Over IP – HD Video Encoder Subsystem
This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of motion JPEG…
The LDS SATA 2 HOST_C5GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Match FIFO on a ALTERA C…
Hardware RTP Stack for JPEG Stream Encapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates JPEG streams to RTP packets compliant with RFC 2…
The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave processor interface and a 32-bit master int…
Single Port SRAM compiler - TSMC 90 nm uLL - Memory optimized for high density and speed - Dual Voltage - Compiler range up to 64…
Single Port SRAM compiler - TSMC 55 nm LP - Memory optimized for high density and low power - Deep N Well supported - compiler ra…
Foundry sponsored - Single Port SRAM compiler - TSMC 55 nm HV - Memory optimized for ultra high density and low power - 3ML- comp…
Dual Port SRAM compiler - TSMC 55 nm uLPeFlash - Memory optimized for high density and low power - Dual Voltage - compiler range …