40LP High density dual port SRAM compiler with Vss booster feature
40LP High density dual port SRAM compiler with Vss booster feature
- UMC
- 40nm
- LP
- Pre-Silicon
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
40LP High density dual port SRAM compiler with Vss booster feature
40LP High density dual port SRAM compiler with Vss booster feature
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with ROW redundancy with LVt peripheral
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT
UMC 40nm LP Logic Process standard synchronous high density dual port SRAM memory compiler with LVT
UMC 28nm HPC process Dual Port SRAM with row reapir
UMC 28nm HPC process Dual Port SRAM with row reapir
UMC 28nm HPC process Dual Port SRAM with row repair & LVT
UMC 28nm HPC process Dual Port SRAM with row repair & LVT
UMC 28nm HPC process Dual Port SRAM with LVT
UMC 28nm HPC process Dual Port SRAM with LVT
UMC 28nm HPC process Dual Port SRAM compiler
UMC 28nm HPC process Dual Port SRAM compiler
UMC 40nm Low Power Process , Two Port Register File with dual power rail
UMC 40nm Low Power Process , Two Port Register File with dual power rail
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process;Single-Port SRAM compiler
UMC 55nm eHV process;Single-Port SRAM compiler
ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process.
ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process.
ULL Single Port SRAM with peri HVT, UMC 40nm LP process.
ULL Single Port SRAM with peri HVT, UMC 40nm LP process.
UMC 40nm Low Power Process Single-Port SRAM for dual power rail
UMC 40nm Low Power Process Single-Port SRAM for dual power rail