Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The DDR4 multiPHY is a mixed-signal IP solution designed to provide LPDDR3/LPDDR2/DDR3/DDR3U/DDR3L/DDR4 SDRAM connectivity in a S…
The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…
The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…
The XAUI PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI …
The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…
The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …
The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…
The MIPI D-PHY RX 2/4 Lanes macro implements the physical layer of universal lanes for the MIPI D-PHY interface, stacked in a two…
The MIPI D-PHY Bidirectional 2-Lane(4-Lane) macro implements the physical layer of bidirectional universal lanes for the MIPI D-P…
The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …
The USB 2.0 PHY is a mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to…
>96 dB over 10 Hz bandwidth,
10b ENOB,
92 dBA dynamic range,
The Intra-panel TX PHY IP is a low-power transmitter designed for COG (Chip-on-Glass) and COF (Chip-on-Film) display modules.
SpaceFibre and WizardLink Interface
The GRHSSL IP Core is a versatile and configurable high-speed serial link controller written in VHDL, capable of implementing a S…
Fully compliant with USB 3.2 Gen2x1 featuring PIPE 4.3 and USB 2.0 with a UTMI+ interface; Supports host, peripheral, and dual-role applications
High performance image signal processing for auto and industrial markets
PCIE Gen6 digital controller (Dual Mode)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.
PCIE Gen6 digital controller (Root Complex)
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links.