AES - Encrypts sensitive data to ensure secure communication and transactions
AES ( Encryption Standard) is a widely-used encryption algorithm designed to secure sensitive data.
- AES
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
AES - Encrypts sensitive data to ensure secure communication and transactions
AES ( Encryption Standard) is a widely-used encryption algorithm designed to secure sensitive data.
100G UDP Offload Engine - Offloads UDP packet processing for efficient, high-speed networking
The 100G UDP Offload Engine in Verification IP (VIP) offloads UDP packet processing to specialized hardware, enhancing data trans…
100G TCP/IP Offload Engine - Validates high-speed network traffic, optimizing flow and reliability
The 100G TCP/IP Offload Engine is a cutting-edge Verification IP designed to streamline the testing of high-speed networking inte…
ISO26262 ASIL-B/D Compliant 32-bit RISC-V Core
The AndesCore™ D23-SE is a 32-bit 3-stage pipeline CPU IP core based on AndeStar™ V5 architecture for embedded applications with …
ARINC 664 (AFDX) End System DO-254 IP Core
The ARINC 664 (AFDX) End System DO-254 IP Core (AFDX ES IP) implements an AFDX End System as specified in ARINC 664 Part 7 “Avion…
SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard.
AES-256SS IP specializes in ultra-high throughput and ultra-low latency.
The NeuraScale Scalable Switch Fabric is a WeaveIP™ system IP solution that is designed from the ground-up to provide non-blockin…
The BSi Bluetooth Low Energy IP is an extremely energy-efficient solution with low MIPs and a low gate count.
The BSi12000 series – maximize performance with a space-saving, power-efficient architecture achieved through integrated RF, mode…
The CXL/PCIe Controller IP carries out CXL 3.0 specification and is backward compatible to CXL 2.0 and 1.1.
SGC21713_IP007708_GF_22FDX can be used in a control loop to minimize the voltage for a given frequency or maximize frequency for …
SGC21549_IP007702_GF_22FDX is a digitally controlled RC based oscillator with embedded Physically Unclonable Function (PUF) imple…
LDO – DIFFERENTIAL FEEDBACK REGULATOR
SGC76050_IP007706_GF_22FDX is a low-dropout, fast response, differential feedback linear regulator for integration on SoC.
Best-in-class eUSB2v2 Verification IP for your IP, SoC, and system-level design testing.
xSPI in production since 2019 for many production designs.The Cadence® Memory Model Verification IP (VIP) for xSPI provides verif…
Used by all top market leaders semiconductor companies.The Cadence® Verification IP (VIP) for USB4 provides a capable verificatio…
The Cadence® Verification IP (VIP) for USB is a VIP solution for the Universal Serial Bus Revision 3.2 Specification and errata.
In production since 2012 on multiple production designs.This Cadence® Verification IP (VIP) supports the JEDEC Universal Flash St…
Best-in-Class UCIe Verification IP for your IP, SoC, and System-Level Design Testing The Cadence Verification IP (VIP) for Univer…