The SLVS-EC RX PHY IP is a high-speed, low-power receiver macro compliant with SLVS-EC v3.0 specification, enabling reliable para…
- SLVS-EC
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The SLVS-EC RX PHY IP is a high-speed, low-power receiver macro compliant with SLVS-EC v3.0 specification, enabling reliable para…
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
The UCIe PHY IP enables high-bandwidth, low-latency die-to-die communication across chiplets, fully compliant with the Universal …
The Gold Standard Memory Model is intended to be compatible with the anticipated JEDEC LPDDR6 standard for your IP, Subsystem, So…
Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Silicon Creations supports customers in designing ICs for the automotive market by offering its comprehensive product portfolio t…
The TS_CAN_3V3_X8 is a 3.3V CAN transceiver, which supports data rates up to 1Mbps and is compatible with ISO 11898-2 compliant C…
The Controller Area Network (CAN) is a reliable serial bus protocol defined in the Bosch CAN specifications for standard CAN 2.0B…
Simulation VIP for Ethernet UEC
Best-in-class Ethernet Verification IP for your IP, SoC, and System-level Design Testing The Cadence Verification IP (VIP) for Et…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC sta…
The MIPI SoundWire I3S Manager IP enables efficient, low-power, and high-fidelity audio data transfer for mobile, consumer, and a…
MIPI SoundWire I3S Peripheral IP
The MIPI SoundWire I3S Peripheral IP delivers seamless, low-power, and high-quality audio connectivity for a range of mobile, con…
For sophisticated workloads, DeepTransformCore is optimized for language and vision applications.
Securyzr™ neo Core Platform is Secure-IC’s enhanced version of its flagship offering Securyzr™ integrated Secure Element (iSE) Se…
Revolutionary dataflow architecture optimized for AI workloads with spatial compute arrays, intelligent memory hierarchies, and r…
50MHz to 800MHz Integer-N RC Phase-Locked Loop on SMIC 55nm LL
055SMIC_PLL_01 forms clock output signal with frequency from 50 to 800MHz.
Single-carrier RF transceiver on TSMC 22nm ULL
Single-carrier RF transceiver on TSMC 22nm ULL
Multi-carrier RF transceiver on TSMC 22nm ULL
Multi-carrier RF transceiver on TSMC 22nm ULL
PCIe PHY and controller solution
Brite 16Gbps PCIe PHY and controller solution provide high efficient interconnection that is optimized for PPA performance.