2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant.
- GlobalFoundries
- 40nm
- Silicon Proven
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
2.5V 5V Tolerant GPIO Inline IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant.
2.5V 5V Tolerant GPIO Staggered IO Pad Set
The 3.3V General Purpose I/O (5VT) library provides programmable bidirectional I/O’s that are both 5V tolerant and fault tolerant.
The LVDS I/O is a three-module design (input, output and reference block).
The LVDS I/O is a three-module design (input, output and reference block).
The SSTL_15/18 pad set is a full complement of I/O, calibration, power, and spacer cells that are necessary to assemble a padring…
1.8V General Purpose Staggered I/O Pad Set
The 1.8V GPIO library provides general purpose bidirectional I/O cells.
3.3V Wide-Range General Purpose Inline I/O Pad Set
The 3.3V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
1.8V General Purpose I/O Staggered Pad Set
The 1.8V General Purpose I/O library provides bidirectional I/O, isolated analog I/O, and a full complement of power cells along …
3.3V General Purpose I/O Inline Pad Set
The 3.3V GPIO library provides general purpose bidirectional I/O cells.
3.3V General Purpose I/O Staggered Pad Set
The 3.3V GPIO library provides general purpose bidirectional I/O cells.
3.3V 100MHz Oscillator IO Inline Pad Set
The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell.
3.3V 100MHz Oscillator IO Staggered Pad Set
The 3.3V 100MHz Oscillators library provides a 100 MHz crystal oscillator macro I/O cell.
3.3V 32kHz Oscillator IO Inline Pad Set
The 3.3V 32kHz Oscillators library provides a 32kHz real time clock oscillator macro I/O cell.
3.3V 32kHz Oscillator IO Staggered Pad Set
The 3.3V 32kHz Oscillators library provides a 32kHz real time clock oscillator macro I/O cell.
3.3V Fault Tolerant General Purpose I/O Inline Pad Set
The 3.3V GPIO FT library provides general purpose bidirectional I/O cells that are fault tolerant.
3.3V Fault Tolerant General Purpose I/O Staggered Pad Set
The 3.3V GPIO FT library provides general purpose bidirectional I/O cells that are fault tolerant.
The LVDS library provides an LVDS driver, receiver, and temperature stable voltage reference capable of supporting 16 drivers ope…
1.8V General Purpose I/O Staggered Pad Set
The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells.
1.8V General Purpose I/O Staggered Pad Set
The 1.8V GPIO FT library provides ultra low leakage general purpose bidirectional I/O cells.
MIPI CSI-2 Receiver v2.0 Controller IP, Compatible with MIPI C-PHY & D-PHY
The CSI-2 Receiver IP is in charge of handling CSI2 & SMIA protocols, as well as depacking input data to pixels.