10-bit, 500 MSPS SAR ADC - STMicroelectronics 28nm
The A10B500M is an ultra-low-power and high-speed analog to digital converter (ADC) intellectual property (IP) design block.
- 10 Bit
10-bit, 500 MSPS SAR ADC - STMicroelectronics 28nm
The A10B500M is an ultra-low-power and high-speed analog to digital converter (ADC) intellectual property (IP) design block.
The A10B320M is an ultra-low-power and high-speed analog to digital converter (ADC) intellectual property (IP) design block.
10-bit, 50 MSPS Pipeline ADC - X-Fab 180 nm
The A10B50M is an ultra low-power analog to digital converter (ADC) intellectual property (IP) design block.
The A10B3M is an ultra-low-power and medium-speed analog to digital converter (ADC) intellectual property (IP) design block.
6-bit, 20 GSPS Flash ADC - STMicroelectronics 28nm
The A6B20G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
The A6B10G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block.
64X1 Bits OTP (One-Time Programmable) IP, GF 22nm FDX 0.8V/1.8V Process
The AT64X1G22GN0AA is organized as a 64-bit by 1 one-time programmable (OTP).
Samsung 28nm Low Voltage Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Voltage Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexib…
Samsung 28nm Low Power Single-Port SRAM Compiler
VeriSilicon Samsung 28FDSOI Low Power Synchronous Single-Port SRAM compiler optimized for Samsung FDSOI 28nm process can flexibly…
Adaptive Body Bias Generator on Samsung 28nm LN28FDS
The adaptive body bias generator (ABBG) consists of a positive-BBG and a negative-BBG for FDSOI-MOS transistors.
802.11ah RF IP is a radio system for signal transmission and reception over wireless channels on the 863-928 MHz ISM frequency ba…