The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA…
- Protocol Bridge
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The Roa Logic AHB-Lite APB4 Bridge is a fully parameterized soft IP interconnect bridge between the AMBA 3 AHB-Lite v1.0 and AMBA…
In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps …
The IntelliProp IPP-NV186A-BR is an NVMe-to-SATA Bridge that utilizes the IntelliProp NVMe Target IP Core and the IntelliProp SAT…
The IntelliProp IPC-NV171B-BR NVMe Bridge utilizes the IntelliProp NVMe Host Accelerator Core and the IntelliProp NVMe Target Cor…
MIPI CSI2 rev 2.0 transmitter/controller for FPGA, with 8 lanes and 2.5Gbps per lane
The SVTPlus-CSI2-F is a second generation MIPI CSI2-Tx transmitter IP core for FPGA implementations.
The K-best decoder is part of the MIMO decoder.
The K-best decoder is part of the MIMO decoder.
Encryption and Decryption are fed with an input of 128 bits length and an initial key of one of the supported key lengths (128, 1…
In order to achieve higher throughput, the turbo decoder uses up to 8-parallel MAP decoder.
In the downlink transmission, the physical downlink shared channel (PDSCH) carries the user data (Transport block).
In Digital video broadcasting for cable systems systems, a FEC sub-system is needed.
In Digital video broadcasting for digital transmission for satellite applications, a FEC sub-system is needed.
Display Port v1.4 Rx PHY & Controller IP, Silicon Proven in TSMC 28HPC+
Display port 1.4 Rx IP supports Channel bandwidth Up to 5.4bps per channel (HBR2), Programmable analog characteristics like CDR B…
TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications.
TC5100 is a flexible LDPC encoder/decoder Core.
The ntAES_XTS IP Core is fully compliant with AES-XTS algorithm standardized at NIST SP800-38E and IEEE 1619-2007 recommendations…
DPDK-aware FPGA/GPP data mover
Arkville provides a high-throughput line-rate agnostic conduit between FPGA hardware and GPP software.
The Arm® Cortex®-A55 is the most power efficient mid-range application CPU built on Arm DynamIQ technology.
ARM® Mali™-G72 is the second generation Bifrost-based GPU for High Performance products.
Configurable CAN Bus Controller IP with Flexible Data-Rate
The Controller Area Network (CAN) is widely used in automotive and industrial applications.