Bluetooth Dual Mode v4.2 RF Transceiver IP
This RF transceiver IP is the design data base of a Bluetooth Dual Mode RF Transceiver extracted from a 40nm production chip.
- RF Transceiver
- In Production
- Immediate
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Bluetooth Dual Mode v4.2 RF Transceiver IP
This RF transceiver IP is the design data base of a Bluetooth Dual Mode RF Transceiver extracted from a 40nm production chip.
Narrow band - IoT Ultra-Low power UE RF Transceiver IP
This is an ultra-low-power Cat-M/NB1 UE RF Transceiver IP solution optimized for IoT and M2M applications.
The Arm® Cortex®-A75 - latest and highest-performance application CPU delivering ground-breaking performance and market- power ef…
10b-160MHz-ADC-(802.11 AC AFE)-IP
This ADC is a Dual Low area, Low Power 160 MHz,10 bit Pipelined Analog-to-Digital converter with internal reference.
CoaXPress Multi-Device Multi-Stream Host
The CoaXPress standard defines a cost effective and easy interfacing between video devices and acquisition hardware over RG59 and…
CoaXPress Multi-Link Multi-Stream Device
The CoaXPress standard defines a cost effective and easy interfacing between video devices and acquisition hardware over RG59 and…
The MVD DVB-CSA Scrambler core allows to encrypt MPEG-TS stream using ETSI specified DVB Common Scrambling Algorithm (CSA2).
Auxiliary ADC - 12-bit Successive Approximation Register (SAR) ADC
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution.
WiFi HaLow adapts the familiar WiFi standard to a frequency and connection style that is ideally suited to the Internet of Everyt…
Hantro VC9000E enables 8K encoding with a competitive PPA and high video quality single-core solution supporting AV1, HEVC, H.264…
Display Stream Compression (DSC 1.2) Decoder
The Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions from …
32-bit High Performance Single/Multicore RISC System-on-Chip
The CC100-S is a synthesisable Verilog model of a high performance 32-bit RISC processor based System-on-Chip.
High Channel Count DMA IP Core for PCI-Express
The High Channel Count (HCC) DMA IP core for PCI-Express is a PCIe Endpoint with multiple industry standard AXI Interfaces.
Dolphin Design offers a Reusable Power Kit Library, toward three objectives: To standardize and ease Power Management Network int…
32-bit High Performance Single/Multicore RISC Processor
The CC100-C processor is a synthesisable Verilog model of a high performance 32-bit RISC processor.
The CMS0071 ISDB-S3 Demodulator is a high-performance (A)PSK demodulator core intended for ARIB STD-B44 ISDB-S3 wide band digital…
The Commsonic CMS0070 ISDB-S3 Modulator with integrated LDPC encoder has been designed specifically to address the requirements o…
Comparator with low-quiescent Hysteresis
qCMPH-LP-RR-[1.62-3.63].01 is designed to extract data from the RF waveform in normal mode operation or to detect the waveform am…
Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
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Linear Regulator, Low-noise optimized for sensitive application such as RF or PLL blocks
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