The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…
PCIe 2.0/ CEI 6G, GF 22FDSOI x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 6G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing needs…
LDPC Encoder / Decoder for 5G and 6G NTN PHY
AccelerComm's LDPC IP cores deliver flight-proven FEC performance for 5G and 6G NTN PHY designs.
SATA 6G PHY in GF (40nm, 28nm)
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
SATA 6G PHY in UMC (40nm, 28nm, 22nm)
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
SATA 6G PHY in SMIC (40nm, 28nm)
The Synopsys IP solution for Serial ATA (SATA) provides the necessary logic to implement and verify designs using the SATA interf…
SATA Host 6G Controller on Kintex 7
The LDS SATA 3 HOST XK7 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Kintex 7 speed grade 2 …
Multiprotocol 10G PHY, TSMC N7 x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC N5 X1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x8, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, TSMC 16FFPLL x4, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
Multiprotocol 10G PHY, TSMC 16FFC x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G MP PHY for PCIe 3.0/USXGMII/SGMII, TSMC 12FFC x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, SS SF5 x2, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
10G PHY for PCIe 3.0, SS SF5 x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
Multiprotocol 10G PHY, SS 8LPU x1, North/South (vertical) poly orientation
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…
MP10, USB 3.1/PCIe 3.0 PHY, GF 22FFDSOI x1, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 1
The multi-lane Multi-Protocol 10G PHY IP is part of a high-performance multi-rate transceiver portfolio, meeting the growing need…