128x16 Bits OTP (One-Time Programmable) IP, X-FAB XR013 2.5V SOI Process
The AT128X16B130XR0BA is organized as 128 words by 16 bits one-time programmable in 16-bit read and 1-bit program modes.
- X-FAB
- 130nm
- XR013
- Available on request
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
128x16 Bits OTP (One-Time Programmable) IP, X-FAB XR013 2.5V SOI Process
The AT128X16B130XR0BA is organized as 128 words by 16 bits one-time programmable in 16-bit read and 1-bit program modes.
8Kx16 Bits OTP (One-Time Programmable) IP, VIS 110nm E-Flash 1.5V/3.3V Process
The ATO008KX16VI110EFM5DA I-fuse® IP is organized as 8Kx16 bits one-time programmable (OTP).
4Kx16 Bits OTP (One-Time Programmable) IP, UMC 110 nm 1.2V/3.3V L110AE Process
The AT4K16U110MAE0DA is organized as a 4K-bits by 16 one-time programmable memory.
DDR3 SDRAM Controller IP with advance feautures package
DDR3 interface provides full support for the DDR3 interface, compatible with JESD79-3F specification and DFI-version 2.0 or highe…
DDR2 interface provides full support for the DDR2 interface, compatible with JESD79-2F specification and DFI-version 2.0 or highe…
DDR Memory Controller IP for low power and high reliability
DDR interface provides full support for the DDR interface, compatible with JESD79F specification and DFI-version 2.0 or higher Sp…
Spatial Audio & Head Tracking Solution
Ceva-RealSpace is a Spatial Audio software solution combining precise 3D rendering and accurate, low-latency head tracking.
3.3 - 4.2V to -3.7V step-down DC/DC converter
180XFAB_DCDC_05 is capable to generate -4.2V ÷ -3.3V (-3.7V typical value) voltage and can maintain 50uA load for -3.7V output.
14-bit 1-channel 40 to 160 MSPS pipeline ADC
065STM_ADC_01 is a high-speed 1-channel 14-bit ADC based on a pipelined architecture.
512x1 Bits OTP (One-Time Programmable) IP, VIS 0.15um BCD Generation-2 Process
The ATO00512X1VI150B252NB is organized as a 512-bit by 1 one-time programmable (OTP).
64x8 Bits OTP (One-Time Programmable) IP, X-FAB 0.18um XH018 Modular Mixed Signal Process
The ATO00064X8XH180TG33NA is organized as a 64-bit by 8 one-time programmable (OTP).
4Kx8 Bits OTP (One-Time Programmable) IP, VIS 0.15µm 1.8V/5V BCD GIII Process
The ATO0004KX8VI150BG33NA is organized as a 4K-bits by 8 one-time programmable.
64x8 Bits OTP (One-Time Programmable) IP, UMC 55nm ULP standard CMOS core logic Process
The AT64X8U55ULP6AA is organized as a 64-word by 8 one-time programmable (OTP).
The ATO00128X8TS055ULP3NA is organized as 128x8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.
1x32 Bits OTP (One-Time Programmable) IP, TSMC 0.18um SiGe BiCMOS 1.8V/3.3V Process
The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP).
768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V Process
The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP).
16Kx33 Bits OTP (One-Time Programmable) IP, TSMC 40LP 1.1V/2.5V Process
The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP).
4Kx9 Bits OTP (One-Time Programmable) IP, GF 12LP+ 0.8V/1.8V Process
The ATO0004KX9GF012LPP8ZA is organized as 4K-bits by 9 one-time programmable (OTP).
512x8 Bits OTP (One-Time Programmable) IP, TSMC 12FFC 0.8V/1.8V Process
The ATO00512X8TS012FFC8EA is organized as 512 bits by 8 one-time programmable (OTP).
For device makers, a small, inexpensive, low-power chip that can run the large AI models is needed to lead the market with their …