The USB3.2 Verification IP provides an effective & efficient way to verify the components connected with USB3.2 interface of an I…
- Verification IP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The USB3.2 Verification IP provides an effective & efficient way to verify the components connected with USB3.2 interface of an I…
ADPLL 2GHz Clock Generator - GLOBALFOUNDRIES 22FDX
All-digital phase locked loop (ADPLL) clock generator for a nominal frequency of 2 GHz (0.8 V).
The DDR PHY is designed to support LPDDR4, LPDDR4x and LPDDR5 SDRAM.
Power-On Reset - Flexible Threshold (0.9–1.6V), Ultra Low Current (210nA) - Silterra 0.16 um
This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.16μm C16G CMOS technology.
Linear Voltage Regulator - High Input Voltage (30V), Output Load up to 5mA
This macro-cell is a general purpose linear voltage regulator core designed for X-FAB 0.35μm XH035 CMOS technology.
IGAHBMX03A is a HBM3 (High Bandwidth Memory) PHY IP compliant to the JEDEC HBM3 DRAM Specification Rev 0.95.
USB3.1 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the USB3.1 transceiver IP with PMA and PCS layer is designed for low power and hi…
JESD204B/204C IP with PHY and MAC layer
With sophisticated architecture and technology, JESD204B /204C IP with PHY and MAC layer is designed for low power and high perfo…
SATA/SAS 3.0 transceiver IP with PMA and PCS layer
With sophisticated architecture and technology, the SATA/SAS transceiver IP with PMA and PCS layer is designed for low power and …
RapidIO is a high performance, low pin count, packet switched, full duplex, system level interconnect architecture.
With sophisticated architecture and technology, the SerDes PHY IP with PMA and PCS layer is designed for low power and high perfo…
With sophisticated architecture and technology, the multi-mode transceiver IP with PMA and PCS layer is designed for low power an…
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
This MIPI D-PHY IP is designed to compliant with the MIPI D-PHY v1.2 specifications.
With sophisticated architecture and technology, the Vendor provides LPDDR5 IP solution with high performance and low power.
With sophisticated architecture and technology, the Vendor provides LPDDR4/4x IP solution with high performance and low power.
With sophisticated architecture and technology, the Vendor provides LPDDR3 IP solution with high performance and low power.
With sophisticated architecture and technology, the Vendor provides LPDDR2 IP solution with high performance and low power.
With sophisticated architecture and technology, the Vendor provides DDR5 IP solution with high performance and low power.
With sophisticated architecture and technology, the Vendor provides DDR4 IP solution with high performance and low power.