HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.
HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.
- SRAM
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.
HJTC 0.11um pflash process standard synchronous high density single port SRAM memory compiler.
HJTC 0.11um uLL/pFlash Single Port SRAM compiler
HJTC 0.11um uLL/pFlash Single Port SRAM compiler
HJTC 0.11um uLL/pFlash via1 ROM memory compiler.
HJTC 0.11um uLL/pFlash via1 ROM memory compiler.
UMC 0.162um eFalsh/LL One Port Register File_x005F_x000D_ memory compiler
UMC 0.162um eFalsh/LL One Port Register File memory compiler
UMC 0.162um eFalsh/LL Single-Port SRAM memory compiler _x005F_x000D_
UMC 0.162um eFalsh/LL Single-Port SRAM memory compiler
HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM
HJTC 0.18um pFlash Process synchronous High Density, Low Power mini single port SRAM
UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler.
UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.
UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
HJTC 0.11um eFlash Process Generic Core Cell Library (porting from FSR0K_D)
Fujitsu 90mm LL-HS process MPCA core cell library [Minimum progeamming layer = M3/4/5 (MUST thin metal layers)]
Fujitsu 90nm LL-UHS process MPCA M345 core cell library
Fujitsu 90nm LL-UHS process MPCA M345 core cell library
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
ID PAD of OTG USB2.0 ; XIP 55LP/RVT LowK Logic Process
5V to 3.3V/1.8V with 80mA/40mA driving capability, Linear Regulator; UMC 0.162um GII process.
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process