WDT Verification IP

Truechip’s WDT Verification IP provides a simple verification solution to verify the components interfacing with the WDT the VIP supports Verilog and System Verilog with Universal Verification Methodology (UVM). WDT compatible UVM based, a BUS monitor. BUS monitor monitors all the transfers that are going on the WDT bus.

• The Watchdog Timer (WDT) regains control in case of system failure to increase application reliability.
• The WDT can generate a reset or an interrupt when the counter reaches a given timeout value.
• Supports 32-bit down counter with the minimal timeout value of 65536.
• Configurable reset or interrupt generation with the given timeout value.
• Supports 8 bytes of reset pulse length configuration.
• The key registers associated with the control of the watch dog timer are the timer control register (TCR) and the timer status register (TSR).

• Available in native SystemVerilog (UVM/OVM/VMM) and Verilog.
• Unique development methodology to ensure highest levels of quality.
• Availability of Conformance and Regression Test Suites.
• 24X5 customer support.
• Unique and customizable licensing models.
• Exhaustive set of assertions and cover points with connectivity example for all the components.
• Consistency of interface, installation, operation and documentation across all our VIPs.
• Provide complete solution and easy integration in IP and SoC environment.

• MWDT Driver
• WDT Monitor
• Testbench Configurations
  • Test Suite (Available in Source code)
  • Basic Test Suite
  • Random Test Suite
  • Error Test Suite
  • Assertions & Cover Point Tests
• Integration Guide, User Manual and Release Notes