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Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
ROM
VeriSilicon SMIC 0.18um LL Pro. Syn. VROM Compiler, Memory Array Range:128 to 2Mega Bits
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous programmable Via1 ROM compiler optimized for Semiconductor Manufacturing …
Overview
VeriSilicon SMIC 0.18um Low Leakage Process Synchronous programmable Via1 ROM compiler optimized for Semiconductor Manufacturing International Corporation (SMIC) 0.18um Logic 1P6M Salicide 1.8/3.3V Low leakage process can flexibly generate memory blocks via a friendly GUI or shell commands. The compiler supports a comprehensive range of word length and bit length. While satisfying speed and power requirements, it has been optimized for area efficiency. VeriSilicon SMIC 0.18um Low Leakage Process Synchronous Via1 ROM compiler uses three metal layers within the blocks and supports metal 4, 5 or 6 as the top metal. Dummy bit cells are designed in with the intention to enhance reliability.
Key features
- High Density
- Low leakage
- Size Sensitive Self-time Delay for Fast Access and "Zero" Hold Time
- Automatic Power Down
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| SMIC | 180nm | G | Silicon Proven |
Specifications
Identity
Part Number
SMIC18LL_VROM_01
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
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Frequently asked questions about ROM IP cores
What is VeriSilicon SMIC 0.18um LL Pro. Syn. VROM Compiler, Memory Array Range:128 to 2Mega Bits?
VeriSilicon SMIC 0.18um LL Pro. Syn. VROM Compiler, Memory Array Range:128 to 2Mega Bits is a ROM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for smic Silicon Proven.
How should engineers evaluate this ROM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this ROM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.