Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
USB-C 3.1/DP TX PHY for SS SF5A, North/South Poly Orientation
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
USB-C 3.1/DP TX PHY for Samsung 14LPP, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
USB-C 3.1/DP TX PHY for Samsung 11LPP, North/South Poly Orientation
The USB 3.1 PHY IP provides designers with the industry's best combination of low area and low power with support for the process…
DisplayPort Transmit Controller
The USB-C 3.1/DisplayPort Tx 1.3 Tx IP solution consists of USB-C 3.1/DisplayPort 1.3 PHYs, USB-C 3.1/DisplayPort 1.3 controllers…
DisplayPort 1.4 TX PHY, TSMC N7, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
DisplayPort 1.4 TX PHY, TSMC N4P, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
DisplayPort 1.4 TX PHY, TSMC 16FFC, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
DisplayPort 1.4 TX PHY, TSMC 12FFC, North/South Poly Orientation
The USB-C 3.1/DisplayPort 1.4 IP solution consists of USB-C 3.1/DisplayPort 1.4 PHYs, USB-C 3.1/DisplayPort 1.4 controllers (Devi…
Die-to-Die, High Bandwidth Interconnect PHY Ported to TSMC N7 X24
The High-Bandwidth Interconnect PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
The XSR PHY IP for 112Gbps per lane die-to-die connectivity enables high-bandwidth ultra and extra short reach interfaces in mult…
UCIe-S PHY for Standard Package (x16) in TSMC N6, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x16) in TSMC N4P, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A PHY for Advanced Package (x64) in TSMC N3E, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-S PHY for Standard Package (x32) in TSMC N3P, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …
UCIe-A (Gen2) PHY for Advanced Package (x64) in Intel 18A, North/South Orientation
The UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale …