Synopsys Verification IP (VIP) for Arm® AMBA® AXI™ provides a comprehensive set of protocol, methodology, verification and produc…
- Verification IP
Synopsys is a leading provider of high-quality, silicon-proven semiconductor IP solutions for SoC designs. The broad Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, and signal/power integrity analysis. Synopsys' extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.
Synopsys Verification IP (VIP) for Arm® AMBA® AXI™ provides a comprehensive set of protocol, methodology, verification and produc…
Verification IP for Arm AMBA CHI Protocol
Synopsys Verification IP (VIP) for Arm® AMBA® CHI provides a comprehensive set of protocol, methodology, verification and product…
Verification IP for Arm AMBA ACE Protocol
Synopsys Verification IP (VIP) for Arm® AMBA® ACE provides a comprehensive set of protocol, methodology, verification, and produc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
The LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performanc…
LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC sta…
GF 22FDX 5.5V OTP Auto-Grade1 IO Staggered
Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs.
Designers face the challenge of creating secure, cost-effective, low power, and reliable SoC designs.
Specifications: UAL_200 1.0 Interfaces: 802.3 dj compliant, UPLI DUT Types/Topology: Protocol TL Phy DL Reconciliation Sub Layer…
UCIe Controller add-on CXL2 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller add-on CXL3 Protocol Layer
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
UCIe Controller baseline for Streaming Protocols for ASIL B Compliant, AEC-Q100 Grade 2
The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…
ARC Functional Safety Software
Today’s complex automotive applications require robust safety related hardware and software to meet the increasingly stringent au…
ARC-V RPX Series Functional Safety Processor IP
The ARC-V™ RPX-110 series functional safety (FS) processors, which include the RPX-110-FS, RPX-115-FS, RPX-110V-FS, and RPX-115V-…
Automated Hierarchical Test for Analog/Mixed Signal IPs The SLM SHS IP is an automated hierarchical test solution for efficiently…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…
The ASIL B or D Ready ARC NPX6FS NPUs enable automotive system-on-chip (SoC) designers to accelerate ISO 26262 certification of D…