Faraday Technology IP Cores

DLL-based LVDS RX, UMC 55nm SP/RVT Low-K Logic process.

• UMC
• 90nm
• SP

2.5V LVDS Transmitter 700Mbps, UMC 55nm SP Low-K Logic process.

• UMC
• 90nm
• SP

LVDS TX Pad, UMC 0.35um Logic process.

• UMC
• 90nm
• SP

8M~135MHz DLL-based LVDS TX, UMC 0.13um HS/FSG process.

• UMC
• 130nm
• HS

DLL-based LVDS RX, VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation frequency, UMC 0.13um HS FSG Logic process.

• UMC
• 180nm
• G

UMC 90nm LL/RVT Low-K process with 2.5V device Analog esd IO group.

• UMC
• 90nm
• LL

UMC 90nm LL/RVT Low-K process 1.2V Analogesd set.

• UMC
• 90nm
• LL

UMC 90nm 1.2V LL/RVT Low-K process Analog esd IO group.

• UMC
• 90nm
• LL

UMC 90nm SP/RVT Logic process true 2.5V Analog ESD IO group cell.

• UMC
• 90nm
• SP

UMC 90nm SP process 2.5V Analog ESD IO set ( using 2.5V gate oxide).

• UMC
• 90nm
• SP

UMC 90nm SP/RVT Low-K Logic process True 3.3V Low frequency OSC IO Cell Library.

• UMC
• 90nm
• SP

UMC 90nm SP/RVT Low-K process 1.0V AnalogESD set.

• UMC
• 90nm
• SP

UMC 90nm SP/RVT Low-K process 1.0V Analog esd IO group.

• UMC
• 90nm
• SP

UMC 65nm SP/RVT Low-K Logic process 2.5VOD3.3V PCI-X IO Cell Library.

• UMC
• 65nm

UMC 0.25um Logic process 3.3V Analog ESD IO Set.

• UMC
• 250nm

UMC 0.18um GII Logic process true 3.3V PC133 SDR SDRAM IO cells.

• UMC
• 180nm
• G

UMC 0.18um LL Logic process true 3.3V OSC Low frequency IO Cell Library.

• UMC
• 180nm
• LL

UMC 0.18um LL Logic process true 3.3V OSC High frequency IO Cell Library.

• UMC
• 180nm
• LL

UMC 0.18um e-flash process 1.8V low frequency OSC Pad.

• UMC
• 180nm

UMC 0.18um e-flash process 1.8V high frequency OSC Pad.

• UMC
• 180nm