Faraday Technology IP Cores

UMC 55nm LP Logic process Via1 ROM memory compiler.

• UMC
• 55nm
• LP

UMC 55nm eHV PeriHVT Via1 ROM compiler.

• UMC
• 55nm

UMC 55nm eFlash process with peripheral HVT Pcode ROM compiler.

• UMC
• 55nm

UMC 40 LP/RVT Low-K Logic process Via1 ROM memory compiler.

• UMC
• 40nm
• LP

UMC 0.18um low leakage(LL) Logic process synchronous Via1 ROM memory compiler.

• UMC
• 180nm
• LL

UMC 0.13um CMOS Image SensorCu process ROM compiler.

• UMC
• 130nm
• HS

UMC 0.11um CMOS Image Sensor process 1P3M VIA1 ROM memory compiler.

• UMC
• 110nm

UMC 0.11um EE2PROM/LL process PCode ROM compiler.

• UMC
• 110nm

UMC 0.11um AE/LL eFlash process Via1 ROM compiler.

• UMC
• 110nm
• LL

UMC 0.11um EE2PROM AE LL process Pcode ROM.

• UMC
• 110nm
• LL

UMC 90nm Standard Performance Low-K process Two Port SRAM Register File compiler.

• UMC
• 90nm
• SP

UMC 55nm LP Logic process Synchronous Two Port Register File memory compiler.

• UMC
• 55nm
• LP

UMC 40nm LP/RVT Low-K Logic Two Port Register File memory compiler.

• UMC
• 40nm
• LP

UMC 0.11um HS/FSG Logic process Synchronous Two Port Register File with 339cell memory compiler.

• UMC
• 110nm
• HS

UMC 0.11um AE/LL eFlash process Two Port Register File.

• UMC
• 110nm
• LL

UMC 90nm low leakage Low-K RVT process synchronous One Port Register File memory compiler.

• UMC
• 90nm
• LL

UMC 55nm Standard Performance Low-K Logic process synchronous Single Port Register File SRAM using 0.425-Bit cell memory compiler.

• UMC
• 55nm
• SP

UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler.

• UMC
• 55nm
• LP

UMC 55nm eFlash with peripheral HVT One Port Register File.

• UMC
• 55nm

UMC 40nm LP Logic process Single Port Register File memory compiler with LVT peripheral.

• UMC
• 40nm
• LP