An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
Faraday Technology
•
HQ:
Taiwan
An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process
- UMC
- 55nm
- SP
Compare 2,534 Faraday Technology IP Cores from 1 vendors
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Faraday Technology• HQ: Taiwan
NO External-R ,frequency 30K~60K ,RC Oscillator .
- UMC
- 55nm
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Internal-R, frequency 48MHz/8MHz. Input 1.08V-1.32V; UMC 55nm EFLASH process
Faraday Technology• HQ: TaiwanInternal-R, frequency 48MHz/8MHz.
- UMC
- 55nm
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Faraday Technology• HQ: Taiwan
Self-contained ring oscillator, frequency 32KHz.
- UMC
- 55nm
- LP
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55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,
Faraday Technology• HQ: Taiwan55nm-SP, FPD-Link Receiver, 3.3V/1.0V, 4 data plus 1 clock channel, 16~85MHz, DLL type,
- UMC
- 55nm
- SP
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1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process
Faraday Technology• HQ: Taiwan1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process
- UMC
- 40nm
- LP
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MIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
Faraday Technology• HQ: TaiwanMIPI Transmitter 80~1500MHz combo with CMOS input using MIFS C40LP Logic Process
- Fujitsu
- 40nm
- LP
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MIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
Faraday Technology• HQ: TaiwanMIPI RX 80Mbps~2.5Gbps ; UMC 28nm HPC+ process
- UMC
- 28nm
- HPC+
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Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Faraday Technology• HQ: TaiwanInput 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
- UMC
- 40nm
- LP
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Faraday Technology• HQ: Taiwan
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
- Controller + PHY + 1
- UMC
- 40nm
- LP
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Faraday Technology• HQ: Taiwan
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version…
- Controller + PHY + 1
- UMC
- 40nm
- LP
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DDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
Faraday Technology• HQ: TaiwanDDR3 RTL Digitalize PHY DATA block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
- Controller + PHY + 1
- DDR3
- UMC
- 28nm
- HPC
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DDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
Faraday Technology• HQ: TaiwanDDR3 RTL Digitalize PHY AC block; UMC 28nm HPC/RVT Logic Process using FSJ0C_ARS
- Controller + PHY + 1
- DDR3
- UMC
- 28nm
- HPC
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Faraday Technology• HQ: Taiwan
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 55nm
- LP
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Faraday Technology• HQ: Taiwan
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 55nm
- LP
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Faraday Technology• HQ: Taiwan
Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for SIP Application; UMC 28nm HPC/RVT LowK Logic Process; Vertical v…
- Controller + PHY + 1
- UMC
- 28nm
- HPC
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Compensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
Faraday Technology• HQ: TaiwanCompensation Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY; UMC 55nm LP/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 55nm
- LP
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Faraday Technology• HQ: Taiwan
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 55nm
- LP
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Faraday Technology• HQ: Taiwan
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
- Controller + PHY + 1
- UMC
- 55nm
- LP
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Faraday Technology• HQ: Taiwan
Input 400M-1600MHz, output 400M-1600MHz, all digital slave delay line of FXADDLL340HH0L to generate 25% delay in period of FREF, …
- UMC
- 40nm
- LP