RC Oscillator IP, Output: 70MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
- UMC
- 130nm
- HS
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035.
RC Oscillator IP, Output: 70MHz, UMC 0.13um HS/FSG process
Internal-RC, trimmable fixed frequency 70MHz.
DDR DLL IP, 100MHz - 400MHz, Output: 25% Delay, UMC 0.13um HS/FSG process
DLL-based cell that generates two-channel DQS with 25% timing delay for DDR2 SDRAM controller usage, UMC 0.13um HS/FSG process.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um LL/FSG process
UMC 0.11um low leakage process Standard Core Cell Library Mini-Library.
Single Port SRAM Compiler IP, UMC 90nm SP process
UMC 90nm SP Low-K Logic process Low Power synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 65nm SP process
UMC 65nm standard performance Logic process synchronous extra high speed Single Port SRAM memory compiler.
One Port Register File Compiler IP, UMC 65nm SP process
UMC 65nm standard performance process synchronous high density Single Port Register File SRAM memory compiler.
ROM Compiler IP, UMC 65nm SP process
UMC 65nm SPRVT Logic process synchronous VIA1 ROM memory compiler.
Dual Port SRAM Compiler IP, Support Repair Features, UMC 65nm SP process
UMC 65nm SP/RVT Logic and HVT Low-K process synchronous, high density, Dual Port SRAM compiler with the row redundancy option.
DC-DC IP, Input: 3.3V, Output: 5V/50mA, UMC 65nm LL process
DC-DC Power converter, Input:3.0V~3.6V, output:5V, 50mA loading, UMC 65nm LL/RVT Low_K process.
PLL (Frequency Synthesizer) IP, Input: 20MHz - 200MHz, Output: 300MHz - 600MHz, UMC 65nm LL process
Input 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 65nm LL Logic/RVT Low-K process.
PLL (Frequency Synthesizer) IP, Input: 5MHz - 500MHz, Output: 31.25MHz - 500MHz, UMC 65nm SP process
Input 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.
One Port Register File Compiler IP, UMC 0.11um CIS process
UMC 0.11um CMOS Image Sensor 2P3M process synchronous high density Single Port Register File SRAM memory compiler.
Standard Cell (Generic) Library IP, HVT, 9 tracks, UMC 90nm LL process
UMC 90nm LL Logic-HVT process standard Core Cell Library.
Band Gap IP, Input: 1.0V - 1.5V, VBG=0.615V, UMC 0.13um HS/FSG process
Input 1.0V-1.5V, VBG=0.615V, Bnad Gap, HS process, UMC 0.13um HS/FSG Logic process.
Linear Regulator IP, Input: 3.3V, Output: 1.2V/1.0V/0.8V, 50mA, UMC 0.13um HS/FSG process
3.3V to 1.2V, 1.0V and 0.8V with 50mA driving capability for each, Istb=130uA, Linear Regulator.
USB 2.0 OTG PHY IP, UMC 0.13um LL/FSG process
USB 2.0 On-The-Go PHY, UMC 0.13um LL process.
Specialty OSC IO IP, UMC 0.11um LL/FSG process
UMC 0.11um LL Logic/FSG process 3.3V low frequency crystal osc.
Specialty OSC IO IP, UMC 0.11um LL/FSG process
UMC 0.11um LL Logic/FSG process 3.3V high frequency crystal osc.
Specialty Analog ESD IO IP, UMC 0.11um LL/FSG process
UMC 0.11um LL Logic process true 3.3V Analog ESD IO.
Specialty OSC IO IP, UMC 0.11um HS/FSG process
UMC 0.11um HS/FSG Logic process 3.3V low frequency crystal osc.