TSMC N5 3DIO Library

Synopsys 3DIO IP Solution is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable, integrated multi-die design structures targeting HPC (AI), GPU, CPU, and mobile applications. The optimal area of the 3DIO IP is carefully designed to be within the BUMP, providing significant advantages in implementation and signal routing.

Synopsys 3DIO IP Solution is architected to support 2.5D, 3D and SoIC package form factors, with flexible physical dimensions on u-BUMP or TSV integration. It comprises a portfolio of 3DIO IP products enabling various use cases: Synthesizable 3DIO for automated placements of thousands of IOs on the bumps, Source Synchronous 3DIO (SS3DIO) for building custom macros, and fully integrated 3DIO-PHY for high performance and fast time-to-market. Synopsys 3DIO IP Solution is part of the Synopsys IP offering for Multi-Die Solutions including UCIe (PHY, Controller, VIP) and HBM3 IP.

The Synopsys 3DIO IP Solution enables designers to create efficient chips in a faster time to market, accelerated with Synopsys 3DIC Compiler to ease integration and provide optimized power, performance, and area (PPA) for a given technology.

• Optimized for heterogeneous integration in 3D stacking
• Enabling designers the flexibility & scalability to accelerate multi-die integration
• Optimal PPA architected to support 2.5D and 3D packages
• Versatile IP offerings tuned for various use scenarios, comprising:
• Synthesizable 3DIO for flexible physical implementation
• Source Synchronous 3DIO (SS3DIO) for building customized macros
• Fully integrated 3DIO PHY for optimal performance
• Compact integrated design, for smallest power & area (<50% of the hybrid bump pitch)
• Compatible with 3DIC Compiler, for fast timing closure