Overview
This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core internal SAR ADC, 8-1 MUX and touch screen drivers. The internal SAR ADC includes sample/hold circuits, a capacitive DAC, a comparator and logic control circuits.
External reference or internal reference is needed. In addition, the reference voltage input will be adjusted to allow encoding smaller analog voltage spanning to the full 12 bits of resolution.
The ADC has dual speed modes – 1M or 200K - working in 200K mode could save some power. Moreover, it supports two running modes: free running and single running. In single running mode, SAR will switch to power down mode automatically so as to save power.
The ADC is especially suitable to act as Touch Screen Controller, demanding less off-chip components to complete the design.
Battery voltage detection could be easily accomplished by the SAR ADC. It has an in-chip resistor divider. Keypad interrupt signal generator is integrated in this SAR ADC too.
The converter has flexible control logic, and could be easily embedded in a complex system.
It is also suitable for integrated auxiliary codec applications and multi-converter architectures in wireless or battery-operated products.
Learn more about ADC IP core
VeriSilicon today announced its high-performance CPP2000 Camera Post-Processing (CPP) IP, expanding the company’s Image Signal Processing (ISP) solutions with advanced post-processing capabilities.
VeriSilicon today announced that its VC9800D Video Processing Unit (VPU) IP supports AV2 decoding, further expanding the company’s advanced video codec portfolio for next-generation video and streaming applications.
VeriSilicon’s Mature GPU, Display Processing, and DeWarp IPs Collaboratively Enable Highly Integrated, Low-Latency AR Display Processing
These enhanced IPs have successfully achieved ISO 26262 ASIL B functional safety certifications issued by TÜV NORD, an international inspection and certification institution, further validating their suitability and reliability for ADAS and autonomous driving applications.
This IP features an architecture streamlined for seamless SoC integration, delivering high-quality inference with low power consumption and a compact silicon footprint. The certificate was issued by SGS-TÜV Saar, an international testing, inspection and certification institution.
The Coral NPU is built on the open RISC-V instruction set architecture, featuring native tensor processing capabilities, supporting mainstream machine learning frameworks such as JAX, PyTorch, and TensorFlow Lite (TFLite), and utilizing open-standard tools like Multi-Level Intermediate Representation (MLIR) from the Low Level Virtual Machine (LLVM) project for compiler infrastructure.