Overview
Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic libraries, and I/O solutions, extensively proven in silicon with billions of units shipping in volume production.
Synopsys I/O Library IP provides designers with the input/output operations, functionality and reliability required for their systems targeting mobile, automotive, and high-performance computing (HPC) applications. The IP is silicon proven and is available in multiple foundries and process technologies from 3nm to 22nm.
Synopsys' I/O portfolio includes robust general-purpose I/Os (GPIOs) and specialty I/Os (LVDS, SD/eMMC, I2C, and I3C) helping designers achieve power, performance, and area (PPA) targets for their SoCs, with low risk and fast time-to-market.
Synopsys I/O Libraries offering includes support to multiple I/O bus protocols. Synopsys I/O Libraries enable Industry’s most comprehensive supply voltage range and have robust ESD for improved manufacturability (configurable CDM specs). Synopsys I/Os operate at very high operating frequencies and include the broadest set of features supporting flexible system design. These features include independent power sequencing, fail-safe/fail-tolerance features, programmable current drive with enhanced granularity, slew control, retention, and bus-keeper support. Synopsys I/O Libraries are self-sufficient and include all the required functional cells – GPIO, supply cells, core clamps, power management cells, and supporting cells s (supply, corner spacers, diode breakers, oscillators, terminators). The multi-row ring implementations & unified I/O framing help in overall area optimizations. Synopsys I/O Library IP supports multiple metal stack options and optimizes partner customization as requested.
Learn more about Standard Cell Libraries IP core
This article describes five areas where designers can take advantage of this new process with the latest logic library technology to optimize the performance, power and area of their system on chips (SoCs).
Physical designers moving to lower foundry nodes worry about how to verify and deliver a design that is free of DRC violations while meeting their tape-out schedule. This can be quite challenging given that the number and complexity of DRC rules is increasing and designs are getting bigger. The need for a better understanding of the manufacturing issues during the design phase raises concerns about how to best address these issues.
This paper, aimed at decision makers within product development companies with responsibility for specifying device connectivity, provides an up-to-date report on the status of Certified Wireless USB technology. It explores the favorable economic factors
Standard cells libraries are usually designed to operate at a specific value of supply voltage referred to as “nominal voltage”. This article details the performance trade-offs in terms of power consumption and speed when decreasing power supply voltage, as well as a methodology to determine the lowest value to use.
If someone had predicted fifteen years ago that 28nm would still be the foundation for many new chip designs, the idea might have seemed unlikely. Process technology was advancing rapidly, and the industry’s attention was firmly fixed on shrinking geometries. Each new node promised more transistors, greater integration, and higher performance.
Adaptability is essential for digital twin systems due to constantly evolving environments – Learn how eFPGA hardware enables robust and adaptable systems
