Aragio Solutions Achieves ISO 9001:2015 Certification
Aragio Solutions, an industry leader and full-service provider of semiconductor IO design IP, is pleased to announce today that it has earned ISO 9001 certification.
Vendor:
Aragio Solutions
Category:
GPIO
SSTL_ I/O Pad Set
The SSTL_2 pad set is a full complement of I/O, power, and spacer cells (total of 14 cells) that are necessary to assemble a padr…
Overview
The SSTL_2 pad set is a full complement of I/O, power, and spacer cells (total of 14 cells) that are necessary to assemble a padring by abutment. Since the SSTL_2 normally operates with its own isolated power domain (2.5V), a “rail-splitter” support cell (SPP_RS_005_25V) is included to allow the designer to easily break the lines that should not connect to the rest of the padring, while allowing VDD and VSS to be continuous within the padring.
What’s Included?
- a. Physical abstract in LEF format (.lef)
- b. Timing models in Synopsys Liberty formats (.lib and .db)
- c. Calibre compatible LVS netlist in CDL format (.cdl)
- d. GDSII stream (.gds)
- e. Behavioral Verilog (.v)
- f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
- g. Databook (.pdf)
- h. Library User Guide - ESD Guidelines (.pdf)
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 55nm | 55nm 550 nm | Silicon Proven |
Specifications
Identity
Part Number
RGO_UMC55_25V25_LP_30C_SSTL_2
Vendor
Aragio Solutions
Type
Silicon IP
Provider
HQ:
USA
Learn more about GPIO IP core
Aragio Solutions Offers Suite of Programmable GPIO I/O Libraries Supporting 65nm Common Platform Technology Available for Chartered Customers
ARAGIO announced today the immediate availability of silicon-proven I/O libraries for the 65-nanometer (nm) Common Platform technology process available from Chartered Semiconductor Manufacturing Ltd.
Aragio Solutions Offers Suite of High-Performance Mixed-Signal IP and I/O Libraries Targeted to Advanced Processes from Chartered
Critical IP Components Available on Chartered’s Leading-Edge Manufacturing Platform
Frequently asked questions about GPIO Pad Library IP cores
What is SSTL_ I/O Pad Set?
SSTL_ I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for umc Silicon Proven.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.