Vendor: Aragio Solutions Category: GPIO

SSTL_15 / SSTL_18 Combo I/O Pad Set

The SSTL_15 / SSTL_18 library supports bidirectional single-ended and differential SSTL_15 and SSTL_18 signaling.

Contact Provider Request Datasheet
GlobalFoundries 28nm SLP Silicon Proven View all specifications

Overview

The SSTL_15 / SSTL_18 library supports bidirectional single-ended and differential SSTL_15 and SSTL_18 signaling. The driver/receiver pairs, with embedded power cells, are supplied with a full complement of calibration, voltage reference, power, spacer, and adapter cells to assemble a pad ring by abutment. An included rail splitter allows isolated SSTL domains to be placed in the same pad ring with other power domains while maintaining continuous VDD/VSS in the pad ring for robust ESD protection.

Key features

  • Full DDR3 capability - 800MHz (1600 Mbps)
  • Full DDR2 capability
  • Low Power driving standard DDR3 memories
  • 1.8V FETs
  • Full complement of cells to build padring (20)
  • Full ODT Capability - dynamic 6-Bit PVT calibration (external reference resistor)

What’s Included?

  • a. Physical abstract in LEF format (.lef)
  • b. Timing models in Synopsys Liberty formats (.lib and .db)
  • c. Calibre compatible LVS netlist in CDL format (.cdl)
  • d. GDSII stream (.gds)
  • e. Behavioral Verilog (.v)
  • f. Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • g. Databook (.pdf)
  • h. Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
GlobalFoundries 28nm SLP Silicon Proven

Specifications

Identity

Part Number
RGO_GF28_18V18_SLP_20C_SSTL_15_18
Vendor
Aragio Solutions
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Aragio Solutions

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Frequently asked questions about GPIO Pad Library IP cores

What is SSTL_15 / SSTL_18 Combo I/O Pad Set?

SSTL_15 / SSTL_18 Combo I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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