Learn more about LDO Voltage Regulator IP core
Featuring dedicated hardware acceleration engines and an optimized memory architecture, GCNanoOptimaV significantly enhances graphics rendering performance and memory efficiency, enabling richer and more responsive graphical user interfaces (GUIs) while addressing the stringent resource constraints of wearable applications.
Optimized GLTiny Model Brings Rich 3D Graphics to Resource-Constrained Wearable Devices Powered by OpenGL ES GPUs
VeriSilicon today announced its high-performance CPP2000 Camera Post-Processing (CPP) IP, expanding the company’s Image Signal Processing (ISP) solutions with advanced post-processing capabilities.
VeriSilicon today announced that its VC9800D Video Processing Unit (VPU) IP supports AV2 decoding, further expanding the company’s advanced video codec portfolio for next-generation video and streaming applications.
VeriSilicon’s Mature GPU, Display Processing, and DeWarp IPs Collaboratively Enable Highly Integrated, Low-Latency AR Display Processing
These enhanced IPs have successfully achieved ISO 26262 ASIL B functional safety certifications issued by TÜV NORD, an international inspection and certification institution, further validating their suitability and reliability for ADAS and autonomous driving applications.
