SMBUS Slave IIP

SMBUS Slave interface provides full support for the two-wire SMBUS Slave synchronous serial interface, compatible with SMBUS version 3.1 specification. Through its SMBUS Slave compatibility, it provides a simple interface to a wide range of low-cost devices. SMBUS Slave IIP is proven in FPGA environment. The host interface of the SMBUS Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

SMBUS Slave IIP is supported natively in Verilog and VHDL

• Compliant with SMBus version 3.1 specification.
• Full SMBus Slave Functionality
• Supports Clock stretching to insert wait states
• Supports command code Protocols
• Write Byte/Word
• Read Byte/Word
• Process Call
• Block Write/Read
• Block Write-Block Read Process Call
• Write 32 Protocol
• Read 32 Protocol
• Write 64 Protocol
• Read 64 Protocol
• Supports Non command code Protocols
• Quick Command Protocol
• Send Byte Protocol
• Receive Byte Protocol
• Supports I2C Write/Read command
• Supports Address Resolution Protocol
• Supports SMBus Alert signal and SMBus Suspend signal
• Supports Packet Error Code
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Simple interface allows easy connection to microprocessor/microcontroller devices
• This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262

• Single site license option is provided to companies designing in a single site.
• Multi sites license option is provided to companies designing in multiple sites.
• Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
• Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

• The SMBUS Slave interface is available in Source and netlist products.
• The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
• Easy to use Verilog Test Environment with Verilog Testcases
• Lint, CDC, Synthesis, Simulation Scripts with waiver files
• IP-XACT RDL generated address map
• Firmware code and Linux driver package
• Documentation contains User's Guide and Release notes.
• ISO26262 Safety Manual (SAM) Document
• ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document