Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
UMC 0.25um Logic process synchronous Single Port Low Power SRAM memory compiler.
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 250nm | 250nm 2500 nm | — |
Single Port SRAM Compiler IP, UMC 0.25um process is a SRAM IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.
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