SHA-256 Processor
This core is a fully compliant implementation of the Message Digest Algorithm SHA-256.
Overview
This core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.
The OL_SHA256 core is a fully compliant hardware implementation of the SHA-256 algorithm, suitable for a variety of applications.
The SHA-256 algorithm is an upgraded version of the SHA-1 algorithm and it offers improved security. It operates on message blocks of 512 bits for which a 256-bit (8 x 32-bit words) message digest (hash value) is produced. Corresponding 32-bit words of the hash values from consecutive message blocks are added to each other to form the message of the whole message.
Key features
- FIPS 180-2 compliant.
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- FPGA netlist available for various devices.
Block Diagram
Benefits
- FIPS 180-2 compliant.
- Suitable for data authentication applications.
- Fully synchronous design.
- Available as fully functional and synthesizable VHDL or Verilog soft-core.
- FPGA netlist available for various devices.
Applications
- Electronic Funds Transfer.
- Authenticated Electronic data transfer.
- Encrypted data storage.
Specifications
Identity
Security
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Hash / MAC IP cores
What is SHA-256 Processor?
SHA-256 Processor is a Hash / MAC IP core from Ocean Logic Pty Ltd listed on Semi IP Hub.
How should engineers evaluate this Hash / MAC?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Hash / MAC IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.