Vendor: Aragio Solutions Category: GPIO

SD 3.0 I/O Pad Set

The SD library provides the driver / receiver cell for SD 3.0 signaling.

Contact Provider Request Datasheet
TSMC 16nm Silicon Proven View all specifications

Overview

The SD library provides the driver / receiver cell for SD 3.0 signaling. The library is compliant with the SD Specifications, Part 1, Physical Layer Specification (Revision 3.01, February 18, 2010). It is also compatible with the Embedded Multi-Media Card (eMMC) Electrical Standard (5.1) (JESD84-B51 – February 2015). This library is offered as a supplement to the I/O libraries provided by Aragio Solutions.

What’s Included?

  • Physical abstract in LEF format (.lef)
  • Timing models in Synopsys Liberty formats (.lib and .db)
  • Calibre compatible LVS netlist in CDL format (.cdl)
  • GDSII stream (.gds)
  • Behavioral Verilog (.v)
  • Layout Parasitic Extraction (LPE) SPICE netlist (.spice)
  • Databook (.pdf)
  • Library User Guide - ESD Guidelines (.pdf)

Silicon Options

Foundry Node Process Maturity
TSMC 16nm 16nm 160 nm Silicon Proven

Specifications

Identity

Part Number
RGO_TSMC16_18V33_FFC_20C_SD
Vendor
Aragio Solutions
Type
Silicon IP

Provider

Contact Aragio Solutions

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Frequently asked questions about GPIO Pad Library IP cores

What is SD 3.0 I/O Pad Set?

SD 3.0 I/O Pad Set is a GPIO IP core from Aragio Solutions listed on Semi IP Hub. It is listed with support for tsmc Silicon Proven.

How should engineers evaluate this GPIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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