UPF Constraint coding for SoC - A Case Study
This paper deals with the implementation of UPF for low power SoC design that can encompass several vendor IPs and custom IPs UPF constraints.
Vendor:
HCL Technologies
Category:
SATA Controller
SATA Host Controller
HCLSATAHC26113G core handles data movement between system memory and a SATA device.
Overview
HCLSATAHC26113G core handles data movement between system memory and a SATA device. The core implements transport layer & link layer functions.
HCLSATAHC26113G is fully compliant with SATA 2.6 specification and with the AHCI (Advanced Host Controller Interface) specification 1.1. The core supports both 1.5Gbps and 3Gbps data transfer rates.
The core has a flexible application/system bus interface and currently supports AMBA AHB interface. On the PHY side the core supports SAPIS/Vendor specific interface.
HCLSATAHC26113G implements flow control functions to offload CPU and handles automatic data transfer on the SATA interface.
HCLSATAHC26113G is fully compliant with SATA 2.6 specification and with the AHCI (Advanced Host Controller Interface) specification 1.1. The core supports both 1.5Gbps and 3Gbps data transfer rates.
The core has a flexible application/system bus interface and currently supports AMBA AHB interface. On the PHY side the core supports SAPIS/Vendor specific interface.
HCLSATAHC26113G implements flow control functions to offload CPU and handles automatic data transfer on the SATA interface.
Key features
- SATA Spec Rev2.6 compatible Link and Transport layer
- Supports 1.5Gbps and 3Gbps data rates
- Compliant to AHCI 1.1, support one port
- Supports Native Command Queuing (FPDMA)
- Supports ATAPI commands
- Supports power management functions
- Supports the DMA and PIO commands
- Supports speed negotiation
- Supports Far-end Retimed loopback
- Supports both Near-end & Far-end analog front-end loopback
- 32 bit FIFO-interface between Link layer and Transport layer
- Configurable TX and RX FIFOs
- DMA engine that compliance to AHCI register set
- Supports SAPIS interface at the PHY side (configurable)
- Configurable phy to link interface to 10 / 20 / 40 bits.
- AMBA AHB master/slave interface at the application
- 8b/10b coding on the link layer (option to disable the 8b/10b coding)
- CONT and data scrambling to reduce EMI
- Supports power management
- Supports Interrupt to Host processor
- Implements statistics counters (Optional)
- Supports OOB detection (COMWAKE, COMRESET/COMINIT)
What’s Included?
- Source code – Verilog HDL
- Verification environment – C and Verilog
- Synopsys DC script
- User Manual
- Test case documents
- Coverage report
Specifications
Identity
Part Number
HCLSATAHC26113G
Vendor
HCL Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
Learn more about SATA Controller IP core
Low Power Design in SoC Using Arm IP
This paper discusses about the low power IP components from ARM can help one to realize the low power features in the SoC. It should be noted that this paper does not discuss about the low power concepts or design techniques. Rather, it focuses on the implementation approaches using ARM low power IP.
Formal Property Checking for IP - A Case Study
In this paper we concentrate only on formal analysis using ‘model checking’. The model checking uses assertions (term broadly used to mean assertion, assume, restrict) written in System Verilog Assertions (SVA) language to prove the given design behavior. The focus of the paper is to provide an introductory flow of formal property check, however, the paper uses a real example to explain the flow.
Timing Annotation of UnTimed Functional Models for Architecture Use-Case
This paper provides a brief overview of PV and AV use cases. It also talks about the timing annotation concepts and a case study of annotating an L2CC (Level 2 Cache Controller) model with timing.
High Level Synthesis of JPEG Application Engine
High Level Synthesis (HLS) technology and tools are used to transform high level behavioral model written in C, to synthesizable hardware in RTL . We have evaluated one such commercial HLS tool to create JPEG encoder RTL straight from C algorithm within a very short design time. This paper discusses the steps involved in automatic “Algorithm to RTL” transformation and compares the results with RTL developed using traditional method.
Frequently asked questions about SATA Controller IP
What is SATA Host Controller?
SATA Host Controller is a SATA Controller IP core from HCL Technologies listed on Semi IP Hub.
How should engineers evaluate this SATA Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SATA Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.