Vendor: Altera Category: RapidIO

RapidIO Intel® FPGA IP

Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II Intel offers two distinct Intel® FPGA IPs for …

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Overview

Intel is discontinuing the intellectual property (IP) for RapidIO I and RapidIO II

Intel offers two distinct Intel® FPGA IPs for RapidIO:

  • RapidIO II Intel® FPGA IP complies with the RapidIO Specification Revision 2.2
  • Physical, transport, and logical layer separations (modular architecture)
  • IDLE2 sequence - long control symbol
  • 1.25, 2.5, 3.125, 5.0 and 6.25 Gbaud lane rates with 1X, 2X, and 4X link widths
  • RapidIO Intel® FPGA IP complies with the RapidIO Specification Revisions 1.3 / 2.1
  • Physical, transport, and logical layer separations (modular architecture)
  • IDLE1 sequence - short control symbol
  • 1.25, 2.5, 3.125, and 5.0 Gbaud lane rates with 1X and 4X link widths

For device support details, such as lane rates, link widths, and speed grades, refer to the RapidIO Intel® FPGA IP user guides.

A significant portion of the wireless industry adopts the RapidIO standard as a high-speed interconnect. The RapidIO standard is typically used between digital signal processors as well as between the control plane processors and memory. RapidIO is also gaining acceptance as a backplane interconnect due to its adoption of widely used standards for the electrical characteristics of the physical media attachment (PMA), such as XAUI or CEI for up to 6.25 Gbaud data rate. Intel® FPGAs are also capable of supporting RapidIO Gen3 data rates.

For a system-level integration-ready solution, you can save several months of design time by selecting all RapidIO layers—including features, such as address translation as well as simple Avalon® Memory-Mapped (Avalon-MM) and Avalon® Streaming (Avalon-ST) FIFO interfaces.

Protocol Solution

One of the images shows an example of a system built using the Platform Designer with a Nios® II soft embedded processor as a processing element. The program memory can include “boot code” for system-level enumeration of the various endpoints. The program also configures the capability address registers of the endpoints and the Intel® FPGA IP function.

Key features

  • PHY based on embedded transceivers
  • Easy to use
    • Intellectual property (IP) parameter editor allows easy manual optimization of parameters, such as interface FIFO depths, address translation windows, output differential voltage, and pre-emphasis
    • Easy configuration provides ways to reduce resource utilization to create smaller Intel® FPGA IP function variations depending on application needs
    • Platform Designer for system interconnect
  • Robust solution
    • Endpoint IP core, testbenches with proven interoperability with leading digital signal processor and switch vendors
    • Compliant to RapidIO specification, Revision 1.3 / 2.1 and 2.2

Block Diagram

RapidIO Intel® FPGA IP block diagram

Files

Product Sheet Download

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Specifications

Identity

Part Number
RapidIO Intel® FPGA IP
Vendor
Altera
Type
Silicon IP

Provider

Altera
HQ: USA
Altera, an Intel Company, provides leadership programmable solutions that are easy-to-use and deploy in applications from the cloud to the edge, offering limitless AI possibilities. Our end-to-end broad portfolio of products including FPGAs, CPLDs, Intellectual Property, development tools, System on Modules, SmartNICs and IPUs provide the flexibility to accelerate innovation. Our innovation of programmable logic started in 1983 in Silicon Valley. In 1984, Altera unveiled the world’s first programmable logic device capable of being programmed, erased, and reprogrammed altering the future of innovation.
Contact Altera

Learn more about RapidIO IP core

How to pick a RapidIO switch

Designers have many different options for implementing a RapidIO interconnect. This article outlines the decision factors that designers should consider, organized by project development phases: system design, implementation, system verification, and system evolution. A last section discusses support services, which impact all stages of project development.

Tips for maximizing RapidIO

RapidIO is an open, standards-based interconnection technology for midsize and large embedded systems. It enables packet-switched, peer-to-peer connections among ASICs, DSPs, FPGAs, microprocessors, network processors and backplanes, with speeds of up to

Frequently asked questions about RapidIO IP cores

What is RapidIO Intel® FPGA IP?

RapidIO Intel® FPGA IP is a RapidIO IP core from Altera listed on Semi IP Hub.

How should engineers evaluate this RapidIO?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RapidIO IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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