RapidIO Verification IP (VIP)
The RapidIO Verification IP (VIP) provides capable compliance verification solution for the RapidIO protocol.
Overview
The RapidIO Verification IP (VIP) provides highly capable compliance verification solution for the RapidIO protocol. The RapidIO VIP is system Verilog (SV) based and supports standard Universal Verification Methodology (UVM). It can be easily combined with any other UVM compliant verification components to extend a broader verification environment. The RapidIO VIP uses a layered architecture which is divided in to a Logical, Transport and Physical layers. RapidIO monitors handle protocol checking and fully comply with RapidIO specification. It provides hooks for implementing functional coverage, scoreboard and end to end checker. RapidIO VIP provides extensive compliance test suite which verifies all possible protocol scenarios. It simplifies the verification flow and reduces the verification effort. It can be used to verify designs at IP, SoC or system level setup. Stimulus generation is fully automated and gives large flexibility for user to generate directed and random test scenarios. User can constrain the randomization at different levels and functional coverage helps gauging the effectiveness of the randomization.
Configurable Options
- RapidlO Specification Version
- Baud rate selection
- Lane configuration
- Addressing mode
- Device ID mode
- Idle configuration
VIP Atributes
- Layered architecture
- PE and PL model selection
- Call backs
- Error injection and detection
- Transactions and symbols monitor log
- Multiple levels of verbosity for debugging
- Register Model
Key features
- Supports RapidlO Specification revisions 4.0, 3.2, 3.1, 3.0, 2.2, 2.0 and 1.3
- Supports 1x, 2x, 4x, 8x and 16x lane configurations
- 1.25G, 2.5G, 3.125G, 5G, 6.25G, 10.3125G, 12.5G and 25.78125G lane rates are supported
- Supports all types of packet formats
- Supports all types of IDLE sequences ,control and status symbols
- Supports 66, 50 and 34-bit addressing on the RapidlO interface
- 8, 16 and 32-bit device id are supported
- Supports test pattern generation at all protocol layers
- System Verilog (SV) based environment
- Complies to Universal Verification Methodology (UVM)
Block Diagram
Benefits
- Serial and Parallel Interfaces supported
- 1x, 2x and 4x serial interface
- 64/128/256-bit internal data path
- PBUS interface for configuration register access
- Up to 256 bytes data payload
- Hardware error recovery
- Exhaustive error reporting and handling
- Pass-Through mode of operation for RIO packets up to 288 bytes
- Accept all Mode of operation for fall over support
- 34/50/66b addressing, 8/16/32b Device ID
What’s Included?
- Product Package
- RapidlO Verification IP
- Compliance Test Suite
- Example test bench and scripts
- Documentation
- User Guide
- Quick Guide
- Compliance Test suite Document
Files
Note: some files may require an NDA depending on provider policy.
Specifications
Identity
Provider
Learn more about RapidIO IP core
How to pick a RapidIO switch
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Enter the Inner Sanctum of RapidIO: Part 1
Enter the Inner Sanctum of RapidIO: Part 2
Frequently asked questions about RapidIO IP cores
What is RapidIO Verification IP (VIP)?
RapidIO Verification IP (VIP) is a RapidIO IP core from Mobiveil Inc. listed on Semi IP Hub.
How should engineers evaluate this RapidIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this RapidIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.